1.john Lau_asm-csia_recent Advances In Packaging

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Recent Advances and Trends in Advanced Packaging John H Lau ASM Pacific Technology 852-2619-2757, [email protected] 1 PURPOSES To present the recent advances and new trends in the following semiconductor packaging technologies:  Fan-Out Wafer/Panel-Level Packaging  Flip Chip Technology  3D IC Integration with TSVs  2.5D IC Integration and TSV-less Interposers 2 Fan-Out Wafer/Panel-Level Packaging (1) PATENTS IMPACTING THE SEMICONDUCTOR PACKAGING (2) FAN-OUT WAFER/PANEL-LEVEL PACKAGINGFORMATIONS (A) Chip-First ( Die-Down) (B) Chip-First (Die-Up) (C) Chip-Last (R DL-First) (3) RDL FABRICATIONS (A) Polymer Method (B) PCB/LDI Me thod (C) Cu Damascene Method (4) TSMC InFO-WLP and InFO-PoP vs. Samsung ePoP (5) WAFER vs. PANEL CARRIER (6) NOTES ON DIRECTRIC AND EPOXY MOLD COMPOUND (7) SEMICONDUCTOR and PACKAGING FOR IoTs (SiP) (8) WAFER/PANEL-LEVEL SYSTEM-in-PACKAGE (WLSiP/PLSiP) (9) PACKAGE-FREE LED (EMBEDDED LED CSP) (10) SUMMARY 3 Typical PCBs in Electronic Products One of the packaging functions is to distribute the signals onto and off the IC chips. Molding Compound Solder Bump Au/Cu wire Underfill IC Chip A Package Substrate Solder Joint IC Chip B Via Lead-frame Solder Joint Cu Trace Printed Circuit Board 4 Lau, ECTC-PDC-2005 Patents Impacting the Semiconductor Packaging (Even there are many important patents such as flip chip and TSV, however I think the following 4 impact the semiconductor packaging the most.)  Lead-Frame  Organic Substrate with Solder Balls (BGA)  Fan-In Wafer Level Packaging (WLCSP)  Fan-Out Wafer Level Packaging (FOWLP) 5 Lead-Frame to Fan-Out the Chip Circuitry 6 The first lead-frame patent! 7 Lau, CSR, 19(6), 2015 Chip Circuitry Fan-Out by Lead-Frame Chip Circuitry is Fanned-Out by Lead-Frame to PCB. Silicon Chip Gold Wires PQFP Silicon Chip Lead-Frame PLCC DIP J- Lead SOIC PCB 8 Gull-wing Lead Lau, CSR, 19(6), 2015 Substrate and Solder Balls to Fan-Out the Chip Circuitry 9 10 Lead-Frame is replaced by organic package substrate and solder balls to fan-out The circuitry of Chip is Fan-Out Through Package Substrate and Solder Balls PBGA (plastic ball grid array) Wire bond Over Mold Die Attach Chip Package Substrate Solder Ball Printed Circuit Board 1993, AMKOR led OSATs to license this technology from Motorola. BGA (ball grid array) era began! Package Substrate Chip face down (flip chip) Chip Underfill Solder bump Solder Ball Printed Circuit Board Chip: 4 to 625mm2 Solder ball: ranging from 10s to 1000s Pitch: PBGA:- 0.65, 0.8, 1, to 1.27mm; fcPBGA:- 0.4, 0.5, 0.65, 0.8, 1, to 1.27mm PBGA package size: range from 10mmx10mm, to as large as 55mmx55mm 11 Lau, CSR, 19(6), 2015 Fan-In Wafer-Level Packaging (WLP) The package made from WLP is called: Wafer-Level Chip Scale Package (WLCSP) 12 Fan-in WLP (WLCSP) to eliminate package substrate and underfill. 13 Lau, CSR, 19(6), 2015 In the past 16 years, WLCSP has been used mainly for ICs with:      low pin-counts (≤ 200) pitch ranges from 0.5, 0.4, 0.35, and 0.3mm small die size (≤ 5mm x 5mm) low-cost, low-end, and low-profile high-volume applications IC for Smartphones, Tables, Wearables, NB, Medical such as:      electrostatic discharge / electromagnetic interference protection radio frequency (RF) filtering power management power amplifiers surface acoustic wave / bulk acoustic wave filters            DC/DC converters light-emitting diodes battery and display driver audio/video codecs and amplifiers logic gates electrically erasable programmable read-only memory microcontrollers Bluetooth + frequency modulation (FM) + Wi-Fi combos global positioning system (GPS) baseband radio frequency transceivers 2001, AMKOR led OSATs and Foundries to license this technology from Flip Chip Technologies. WLP (wafer-level packaging) era began! iPhone 7+ Smartphones IC for internet of things (IoTs) such as:   CMOS image sensors MEMS sensors There are > 25 WLCSPs 14 TSMC’s UBM-free integration (UFI) WLCSP NSMD Chip Chip Corner Pad UBM-Free Solder Ball RDL Protection Layer Solder Joint PCB Cu-Pad ) % ( e r u il a F e v it a l u m u C Protection Layer Solder Mask WLCSP: 5.2x5.2mm2 WLCSP: 10.3x10.3mm2 UFI: 5.2x5.2mm2 UFI: 7.2x7.2mm2 UFI: 10.3x10.3mm2 Failure Cycle (cycles) 15 TSMC IEEE/ECTC2016 Fan-Out Wafer Level Packaging (FOWLP) 16 Because of:  Die shrinking  More functionality (more pin outs)  SiP (system-in-package) Not enough spacing for fanningin the pads due to Die shrinking and more functionality Wafer CHIP Die shrink SiP CHIP A CHIP B 17 Fan-out wafer/panel-level packaging! Chip Edge Over Mold Encapsulant CHIP Dielectric PCB Solder Mask (Polyimide) Metal wire Lau, CSR, 19(6), 2015 Metal pad Solder Ball (RDL) 18 RDLs to fan-out the circuitry beyond the chip edges without using a lead-frame or substrate. Fan-Out Wafer-Level Packaging 36a 26a 14b 40 f 34c 22 (Chip) (Chip Edge) 36a (RDL) RDLs to fan-out the circuitry beyond the chip edges. 19 Lau, CSR, 19(6), 2015 Infineon’s US 6,727,576 20 Lau, CSR, 19(6), 2015 Fan-Out Wafer/Panel Level Packaging 21 FOW/PLP Formations  Chip-First (Die-Up)  Chip-First (Die-Down)  Chip-Last (RDL-First) RDL (Redistribution Layer) Fabrication Methods  Polymer Method  PCB/LDI (Laser Direct Imaging)  Cu Damascene 22 Chip-First (Die-Down) Chip-First (Die-Up) Most of the fan-out wafer/panel-level packages in manufacturing today use either one of these formations for portable, mobile, and wearable products. The reconfigured carrier is neither wafer or panel! 23 Lau, et al., CSR 20(3), 2016 Chip-First (Die-Down) also called eWLB (Embedded Wafer Level Ball Grid Array) Infineon’s eWLB Packaging technology licensed by:     ASE STATS ChipPAC NANIUM (acquired by AMKOR) STMicroelectronics Infineon eWLB (wireless operation) acquired by Intel in 2011. eWLB is used to package:        Baseband RF switch/transceiver PMIC Audio codec MCU RF radar Connectivity ICs 24 FOWLP (Chip-First and Face-Down) 2-side (thermal release ) tape Test for KGD and Dice Temporary (wafer or panel) carrier Device Wafer Die-first (face-down) KDG KGD KGD Passivation Al or Cu Pad CHIP EMC (epoxy mold compound) Over mold the reconfigured carrier Remove carrier and tape Build RDLs and mount solder balls RDLs Solder balls Dice the molded wafer or panel EMC KGD into individual packages Lau, et al., CSR 20(3), 2016 RDLs Solder balls CHIP KGD CHIP KGD CHIP 25 FOWLP (Chip-First and Face-Down)– Need a Temporary Carrier Test for KGD (know n-good die) and Dice 2-side (thermal release ) tape Temporary metal wafer/panel carrier Device Wafer KGD Passivation Temporary carrier with 2-side tape Al or Cu Pad KGD Place the KGDs face-down on the 2-side tape on the temporary wafer carrier KDG KGD KGD Temporary metal wafer/panel carrier Reconstituted (reconfigured) Wafer 26 FOWLP (Chip-First and Face-Down)– EMC and Compression Molding KGD KGD KDG EMC KGD Temporary metal carrier EMC (Epoxy Molding Compound) 2-side tape Reconstituted (reconfigured) Wafer 27 FOWLP (Chip-First and Face-Down) – Remove Carrier and Tape, Build RDLs, Ball Mounting, and Dicing EMC Remove carrier and tape KGD Build RDLs and mount solder balls RDLs Solder balls Dice the molded wafer or panel into individual packages EMC KGD CHIP KGD CHIP KGD CHIP CHIP CHIP RDLs Solder balls 28 FOWLP EMC KGD Redistribution Layer (RDL) Solder Ball PCB Package: 5mmx5mm Solder Ball KGD 3mmx3mm RDL EMC 29 Lau, ECTC-PDC-2015 Chip-First (Die-Down) RDLs by Polymer Method 30 Lau, et al., CSR 20(3), 2016 HTC Desire 606W (SPREADTRUM SC8502) Package Size: 7.4 x 7.4 x 0.71mm Modem (2.8 x 2.8mm) 115µm m µ 0 3 4 Apps Processor (3x3mm) PCB Over Mold 2 RDLs: 20µm L/S 230 solder balls @0.4mm pitch 31 Audio Codec (Qualcomm), packaged by STATSChipPac 32 Fan-Out eWLP (Embedded Wafer-Level Packaging) RDLs KGD Pads 33 Solder balls Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) EMC Pad KGD KGD RDLs Dielectric Pad Solder ball KGD KGD EMC Solder ball 34 Lau, ECTC-PDC-2015 Chip-First (Die-Up) 35 FOW/PLP Formation: Chip-First (Die-Up) Test for KGD Coated with a LTHC sacrificial layer Device Wafer UBM Die face-up Temporary (wafer) glass carrier KGD KGD KGD KGD KGD Contact pad CHIP Passivation Al or Cu Pad Sputter UBM and electroplate contact pad UBM LTHC Polymer Contact pad EMC Over mold the reconfigured carrier Backgrind the over-mold to expose the contact pad Solder balls CHIP DAF Polymer on top, die-attach film on bottom of wafer, and dice the wafer RDLs Build RDLs on contact pads and mount solder balls Remove carrier by a laser and then dice the molded wafer or panel into individual packages RDLs Lau, et al., CSR 20(3), 2016 Solder balls KGD 36 FOWLP (Chip-First and Face-Up)– Need a Temporary Carrier Test for KGD Coated with a LTHC (~1µm) layer Device Wafer UBM LTHC Temporary glass wafer carrier DAF KGD Contact pad Place the KGD face-up on the LTHC layer of the glass carrier KGD KGD Temporary glass w afer carrier KGD Passivation Al or Cu Pad Glass carrier coated with a LTHC layer Sputter UBM and electroplate Cu contact pad UBM Polymer Contact pad KGD KGD DAF Polymer on top, die-attach film (DAF) on bottom of the device wafer, and dice the device wafer 37 Lau, ECTC-PDC-2015 Reconstituted (reconfigured) Wafer FOWLP (Chip-First and Face -Up)– EMC and Compression Molding KGD Cu-contact pad EMC KGD KGD KGD EMC (Epoxy Molding Compound) Temporary glass wafer carrier LTHC layer DAF Reconstituted (reconfigured) Wafer 38 Lau, ECTC-PDC-2015 FOWLP (Chip-First and Face-Up) – Backgrind the EMC to expose the Cu-pad, Build RDLs, Mount Solder Balls, Debond the carrier, and dicing Cu-contact pad DAF EMC Backgrind the over-mold to expose the Cu-contact pad LTHC Layer KGD Glass wafer carrier Solder balls RDLs Build RDLs on Cu-contact pads and mount solder balls Remove carrier by a laser and dice the molded reconstituted wafer into individual packages KGD KGD KGD RDLs Solder balls Lau, ECTC-PDC-2015 39 (a) Top-side of the molded (b) Bottom-side of the molded test package on glass test package on glass wafer wafer with LTHC layer. without LTHC layer (a) (b) 40 Polymer UBM Chip-First (Die-Up) RDLs by Polymer Method Contact Pad Cu Pad Passivation Mask aligner or Stepper (Litho) EMC CHIP Polymer, e.g., PI, BCB, or PBO Cu Plating Spin Polymer TiCu RDL1 Polymer Photoresist Mask aligner or Stepper (Litho) Strip Resist & Etch TiCu RDL2 RDL1 Etch Polymer, Strip Resist Sputter TiCu TiCu Contact Pad Solder Ball UBM RDL2 Dielectric2 RDL1 Dielectric1 Photoresist Cu Pad CHIP Polymer UBM Contact Pad Passivation EMC 41 Lau, et al., CSR 20(3), 2016 TSMC’s InFO (Integrated Fan-Out) WLP for Apple’s A10 Application Processor Chip-Frist (Die-Up) 42 Lau, et al., CSR 20(3), 2016 US 9,000,584 B2 (Publication Date: April 7, 2015) PACKAGED SEMICONDUCTOR DEVICE WITH A MOLDING COMPOUND AND A METHOD OF FORMING THE SAME Jing-Cheng Lin, Hsinchu County (TW); Jui-Pin Hung, Hsinchu (TW); Nai-Wei Liu, Fengshan (TW); Yi-Chao Mao, Zhongli (TW); Wan-Ting Shih, Touwu Township (TW); and Tsan-Hua Tung, Hsinchu (TW) Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., (TW) FIG. 1I also shows a more detailed view of the die 104 and the wiring layer 108, in accordance with some embodiments. The view of the die 104 and wiring layer 108 are exemplary; alternatively, the die104 and wiring layer 108 may comprise other configurations, layouts and/or designs. In the embodiment shown, the die 104 includes a substrate 124 comprising silicon or other semiconductive materials. Insulating layers 126 a and 126 b may comprise passivation layers disposed on the substrate 124. Contact pads 128 of the die 104 may be formed over conductive features of the substrate such as metal pads 127, plugs, vias, or conductive lines to make electrical contact with electrical components of the substrate 124, which are not shown. 43 Lau, CSR, 19(6), 2015     KGD UBM Contact pad Polymer DAF Contact pad UBM Contact pad Pad Passivation Pad SiO2 KGD Si Die attach film (a) Polymer Contact pad Pad UBM Passivation SiO2 Contact pad Pad Si KGD Die attach film Temporary round (glass) Carrier (b) LTHC (ligh t to heat conversion) or sacrificial layer 44 Lau, CSR, 19(6), 2015 Polymer EMC Contact pad UBM Contact pad Pad Passivation SiO2 Si Pad KGD Die attach film Temporary round (glass) Carrier (c) Over Mold Polymer Contact pad EMC Pad UBM Contact pad Passivation SiO2 KGD Pad Si Die attach film Temporary round (glass) Carrier (d) 45 Lau, CSR, 19(6), 2015 dl o Mr ev O Passivation RDL RDL UBM UBM Polymer Polymer Contact pad EMC UBM Solder Ball UBM Solder Ball Dielectric Contact pad Passivation SiO2 Pad Pad KGD Si Die attach film Si Temporary round (glass) Carrier (e) Die attach film KGD Si SiO2 Passivation Pad UBM Contact pad EMC Pad Contact pad Polymer Dielectric Passivation RDL RDL Over Mold UBM Solder Ball UBM r e myl o P Solder Ball (f) 46 Lau, CSR, 19(6), 2015 PoP for the Mobile DRAMs and Application Processor of iPhone 7/7+ Wirebond 3-Layer Coreless Package Substrate Over Mold Memory Memory Solder Ball Underfill A10 AP A10 chip size: 11.6mm x 10.8mm x165µm EMC TIV RDLs Solder Ball LPDDR4 Chips Layout in the upper (P oP) Package g g n i n rii d n Wo b 15.5mm x 14.4mm Memory Memory g g in n rii d n Wo b Wiring bonding PoP sizes: 15.5mm x 14.4mm x 825µm Package Chip = 15.5x14.4 11.6x10.8 g n rii W g in d n o b Memory Memory g g n i in ri d n o Wb ~ 1.8 Wiring bonding 47 Lau, CSR, 2017 PoP for the Mobile DRAMs and Application Processor of iPhone 7/7+ Wirebond 3-Layer Coreless Package Substrate Over Mold Memory Memory Solder Ball Underfill A10 AP EMC TIV RDLs A10 chip size: 11.6mm x 10.8mm x165µm Solder Ball LPDDR4 Mobile DRAMs 3L Coreless substrate Underfill 15.5mm x 14.4mm A10 AP Die Solder Ball 386 balls at 0.3mm pitch Package Mold (EMC) TIV (Through InFO Via) 3RDLs Solder Ball PoP sizes: 15.5mm x 14.4mm x 825µm Package Chip = 15.5x14.4 10L PCB ~ 1.8 11.6x10.8 48 Lau, CSR, 2017 ~1300 solder balls at 0.4mm pitch PoP for the Mobile DRAMs and Application Processor of iPhone 7/7+ 3-Layer Coreless Package Substrate Wirebond Over Mold Memory Memory Solder Ball Underfill A10 AP EMC TIV RDLs A10 chip size: 11.6mm x 10.8mm x165µm Solder Ball Wire bond Over mold (~170µm) LPDDR4 Memory (105µm) 15.5mm x 14.4mm 3L substrate (100µm) Underfill Underfill A10 AP (165µm) PoP sizes: 15.5mm x 14.4mm x 825µm 3 RDLs (~50µm) Package Chip Lau, CSR, 2017 = 15.5x14.4 11.6x10.8 ~ 1.8 Contact Pad ~1300 solder balls at 0.4mm pitch Binghamton University/Prismark 49 Significant of the Apple A10 Packaged by TSMC’s FOWLP  Now that we’d seen the cross section of the real thing (Apple’s A10) packaged       with the fan-out wafer-level packaging (FOWLP) technology by TSMC. This is very significant, since Apple and TSMC are the “sheep leaders”. Once they used it, then many others will follow. Also, this means that FOWLP is not just only for packaging baseband, RF switch/transceiver, PMIC, audio codec, MCU, RF radar, connectivity ICs, etc., it can also be used for packaging large (125mm2) SoC such as APs (application Processors). As a matter of fact, a long li st of companies such as HiSilicon, MediaTek, Spreadtrum, Qualcomm and Apple are queuing for TSMC’s 10nm/7nm process technology and their fan-out packaging technology. Other companies such as Samsung are also working on fan-out technology for their and others’ APs. With the popularity of SiP, fan-out (which can handle multiple dies) wil l be used more because the WLCSP can only handle single die. In general, fan-out technologyeliminates the wafer bumping, fluxing, flip chip assembly, cleaning, un derfill dispensing and curing, and package substrate. Eventually, it will lead to a lower profile and cost packaging technology. Fan-out technology will be very popular in the next few years, until the “next new package technology” comes out. 50 Fan-Out Panel-Level Packaging (FOPLP) 51 Wafer vs. Panel (610mm x 457mm) Area > 3.8 X 12”-wafer 12” wafer carrier 24”x18” carrier 52 Lau, CSR, 19(6), 2015 For fan-out wafer/panel packaging, why use panel leads to lower cost?  Because the RDLs of the panel are f abricated by PCB/LDI technology and P&P of dies and passives are by SMT equipment.  Since the area of panel is larger than that of wafer, thus more packages can be made. It should be noted that, fan-out panel wafer level packaging is applied to low-end, low-performance, low pin-count, and small devices. The line width/spacing of the RDLs are >10µm. 53 Lau, CSR, 19(6), 2015 Al Pad + Cu or Ni bump 54 Lau, et al., CSR 20(3), 2016 Process for Panel RDLs by PCB + LDI (Laser Direct Image) Al Pad + Cu or Ni bump Passivation RDL1 Dry film strip and Cu seed etching EMC KGD ABF Lamination of a Ajinomoto Build-up Film (ABF) RDL2 RDL1 Laser drilling Cu Electroless Cu seed layer Surface finish Solder mask Spin coat solder mask and surface finish Photoresist Dry film lamination Laser direct image (LDI) and dry film development Solder ball Solder mask Cu RDL2 ABF RDL1 Cu PCB Cu plating Repeat all the processes to get RDL2 KGD ABF Surface finish Solder ball mount EMC 55 Al or Cu Pad Passivation The geometry, material, process, equipment, and application of fan-out wafer/panel-level packaging EMC Pad KGD KGD RDLs Dielectric Pad Solder ball Solder mask, polymer, or SiO 2 Redistribution Layer Dielectric Reconfigured Appl. width/spacing thick. Mat.(Thick.) carrier Highend Middleend Lowend < 2 - 5µm ≤ 2µm SiO2 (1µm) Litho. Stepper Proc./Equip. _Cu damascene _Semi. Equip. _High-Precision P&P _Cu plating Mask Polymers _Packaging Equip. (4 - 8µm) aligner or Stepper _Ordinary P&P 5 - 10µm ≥ 3µm > 10µm Resin ≥ 5µm (15 - 30µm) Laser direct imaging _PCB Cu plating _PCB Equip. _SMT P&P 56 Lau, CSR, 19(6), 2015 Panel Sizes for FOPLP J-Devices: 320mmx320mm (PCB) Fraunhofer: 610mm x 457mm (PCB) SPIL: Gen 2.5 (370mmx470mm) (LCD) PTI: 370mm x 470mm (LCD) SEMCO: Gen 3.25 (600mm x 720mm) and Gen 4 (730mm x 920mm); ~400mmx500mm (LCD) ASM: 340mmx340mm and 508mmx508mm 57 Embedded Chips in EMC, Laminated, Silicon, and Glass Substrates As you all know that for most of the fan-out wafer-level packaging (FOWLP), the chip(s) are embedded in the epoxy molding compound (EMC) such as eWLB by Infineon and Statchippac and InFO by TSMC. In fan-out panel-level packaging (FOPLP), the chip(s) are embedded in EMC (such as Fraunhofer and J-Devices) and laminated substrate (such as AT&S, Unimicron, and Imbera.) On June 28, 2013 (priority date: March 5, 2013), Maxim Integrated proposed (US 20140252655 A1) to embed the chip(s) in a silicon substrate in their FOWLP, Figure 1. They presented their papers in 2015. On May 31, 2017, George Institute of Technology (GIT) will present the very first demonstration on chip(s) embedded in glass substrate in their FOPLP. 58 Maxim’s Fan-Out Wafer-Level Packaging (Chip Embedded in Silicon Substrate) Khanh Tran, Arkadii V. Samoilov, Pirooz Parvarandeh, Amit S. Kelkar, “Fan-out and heterogeneous packaging of electronic components”, US 20140252655 A1, Filing date: June 28, 2013, Priority date: March 5, 2013. GIT’s Fan-Out Wafer-Level Packaging (Chip Embedded in Glass Substrate) P&P chips on glass cavities Chips on glass cavities Tailong Shi, Chintan Buch, Vanessa Smet, Yoichiro Sato, Lutz Parthier, Frank Wei, Cody Lee, Venky Sundaram, and Rao Tummala, “First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency MultiChip Integration” . To be presented on May 31, 2017 at E CTC. Instead of Wafer, how about use Panel Carrier for Large and High-Performance Chips with Fine Line Width and Spacing package to increase Throughput? Sure! What’s the Standard Size of Panel so the Equipment Company can make the necessary Equipment (e.g., Physical Vapor Deposition, Electrochemical Deposition)? 61 Chip-Last (RDL-First) For very high-density and high-performance applications, e.g., high-end servers, computers, and networking. The reconfigured carrier is wafer! 62 Lau, et al., CSR 20(3), 2016 Chip-Last (RDL-First) Fan-Out Wafer-Level Packaging (FOWLP) Since 2006, NEC Electronics Corporation (nowRenesas Electronics Corporation) has been developing a novel SMAFTI (SMArt chip connection with FeedThrough Interposer) packaging technology for:  inter-chip wide-band data transfer  3D stacked memory integrated on a logic devices  system in wafer-level package (SiWLP) (2010)  and “RDL-first” fan-out wafer-level packaging (2011) The FTI (feedthrough interposer) of SMAFTI is a film with ultra-fine line width and spacing RDLs. The dielectric of the FTI is usuallySiO2 or polymer and the conductor wiring of the RDLs is Cu. The FTI not only supports the RDLs underneath within the chip, it also supports beyond the edges of the chip. Area array solder balls are mounted at the bottom-side of the FTI which are to be connected to the PCB. Epoxy mold compound (EMC) is used to embed the chip and support the RDLs and solder balls. In 2015, Amkor announced a very similar technology called “SWIFTTM” (silicon wafer integrated fan-out technology). 63 Lau, et al., CSR 20(3), 2016 A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology Yoichiro Kurita, Satoshi Matsui, Nobuaki Takahashi, Koji Soejima, Masahiro Komuro, Makoto Itou, Chika Kakegawa, Masaya Kawano, Yoshimi Egawa, Yoshihiro Saeki, Hidekazu Kikuchi, Osamu Kato, Azusa Yanagisawa, Toshiro Mitsuhashi, Masakazu Ishino, Kayoko Shibata, Shiro Uchiyama, Junji Yamada, and Hiroaki Ikeda NEC Electronics, Oki Electric Industry, and Elpida Memory 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan 64 NEC ECTC2007 Chip-last with face-down (die-down) or “RDL-first” FOWLP This is very different from the chip-first FOWLP. First of all, this only works on wafer carrier. Also, comparing to chip-first, RDL-first FOWLP requires:  building up the RDLs on a bare silicon wafer (the FTI),  performing the wafer bumping,  performing the fluxing, chip-to-wafer bonding, and cleaning,  performing the underfill dispensing and curing. Each of these tasks is a huge task and requires additional materials, process, equipment, manufacturing floor space, and personal effort. Thus, comparing to chip-first FOWLP, chip-last (RDL-first) FOWLP incurs very high cost and has more chances to have higher yield losses. It can only be afforded by very-high density and performance applications such as high-end servers and computers. 65 Lau, et al., CSR 20(3), 2016 Chip-Last (RDL-First) Process-Flow RDLs Si-wafer Device Wafer Build RDLs on a bare Si-wafer KGD KGD Cu UBM Solder Contact pad Fluxing, Chip-to-wafer bonding, and cleaning Underfill CHIP Passivation Al or Cu Pad Cu-Pillar Underfill dispensing and curing EMC Contact pad Cu-pillar plating Over mold the reconfigured wafer Metal reinforced wafer Solder cap Cu-Pillar Contact pad CHIP Solder-cap plating After wafer bumping, test for KGDs and dice the wafer Backgrind EMC to expose the backside of the KGDs and attach to a reinforced wafer, then backgrind the Si-wafer KGD KGD Heat spreader EMC Cu-pillar Underfill Solder joint RDL Solder ball 66 Mount solder ball and dice molded wafer Lau, et al., CSR 20(3), 2016 Wafer Bumping Process Flow Solder Cu Cu Passivation Solder TiCu Pad (5) ECD Cu, Solder (7) Etch Cu/Ti Si (9) Schematic Solder Passivation pad Si (6) Strip Resist (1) Redef. Passivation Cu Ti (8) Flux, Reflow UV C4 (controlled collapsed chip connection) bump Mask Passivation Solder (2) Sputter Ti/Cu (10) Image (3) Spin Resist (4) Patterning Solder TiCu Cu Cu Pad (5) ECD Cu, Solder (7) Etch Cu/Ti Si (9) Schematic Solder Cu (6) Strip Resist (8) Flux, Reflow C2 (chip connection) bump Lau, ECTC-PDC-2014 (10) Image 67 Process flow of RDLs by Dual Cu Damascene Method Si wafer SiO2 RIE of SiO2 SiO2 by PECVD Photoresist Strip resist Spin coat Photoresist TiCu Cu Sputter Ti/Cu and Electroplate Cu Stepper, Litho. V01 RDL1 CMP the overburden Cu and Ti/Cu RIE of SiO2 DL2P DL2 DL12 DL1 DL01 DL0 Contact Pad DL2P V12 RDL1 RDL2 SiO2 V01 Si wafer 68 Stepper, Litho. Lau, et al., CSR 20(3), 2016 Repeat the processes to get RDL2 and contact pad Typical SEM Image of RDLs Fabricated by Dual Cu Damascene Method Contact Pad UBM RDL3 V23 RDL2 V12 RDL1 V01 Si wafer 69 Lau, et al., CSR 20(3), 2016 Removing Si-Wafer and Solder Ball Mounting After the assembly, remove the Si wafer and mount solder balls DL2 V12 DL12 DL01 V01 Stepper, Litho. RDL2 DL1 RDL1 RIE of SiO2 Si wafer Repeat the processes to get RDL2 Stepper, Litho. V12 V01 RDL2 RDL1 RIE of SiO2 and strip resist Backgrind and then CMP the Si wafer, TiCu, and passivation Sputter Ti/Cu and electroplate Cu SiO2 by PECVD CMP Cu and Ti/Cu RDL2 V12 V01 Spin coat photoresist UBM RDL1 Solder ball Passivation Contact pad 70 Lau, et al., CSR 20(3), 2016 Solder ball mounting AMKOR’s SWIFT R. Huemoeller, and C. Zwenger, “Silicon wafer integrated fan -out technology”, Chip S cale R eview , March/April Issue, 2015. 71 NOTES ON MOLDING MATERIALS The molding of FOWLP is by the compression method with EMC. For Chip-First FOWLP, the curing temperature of the EMC must be lower than the release temperature of the 2-side tape. For Chip-First and Chip-Last FOWLP:  There are at least two forms of EMC, namely l iquid and solid. The advantages of liquid EMC are better handling, good flowability, fewer voids, better fill, and less flow marks. The of solid EMC are less cure shrinkage, better stand-off, and advantages less die drift.  High filler content (>85%) EMC will shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage.  Uniform filler distribution and filler size of the EMC will reduce flow marks/fill and enhance flowability. Filler content (wt%) Maximum filler size (µm) Mold condition (m/oC) Post cure (h/oC) Tg (oC) Bending stiffness (GP) Sumitomo (solid) 90 55 7/125 1/150 170 30 Nagase (liquid) 85 25 10/125 1/150 150 19 72 Lau, et al., CSR 20(3), 2016 NOTES ON EQUIPMENT Pick and Place (P&P)  SMT/chip shooter P&P for large-pitch KGDs and thus large line width/spacing RDLs, e.g. Universal, Panasonic, and ASM.  High precision P&P for fine-pitch KGDs and thus fine line width/spacing RDLs, e.g. Toray, Datacon, and ASM. RDLs  The seed/adhesion layer by PVD, e.g., Applied Materials, SPTS (now Orbotech) and NEXX.  The dielectric layer by PECVD, e.g., Applied Materials, Lam Research, and Tokyo Electron.  The conductor wiring by ECD, e.g., Semitool (now Applied Materials), Novellus (now Lam Research), and NEXX. Molding Compression with EMC, e.g., Yamada, TOWA, and ASM. Solder Ball Mounting The equipment suppliers are, e.g.,Shibuya, PacTech, and ASM. Packaging Handling Inspection, test, and laser marking are, e.g.,DISCO, Rudolph, and ASM. 73 Lau, et al., CSR 20(3), 2016 WLSiP (Wafer-Level System-in-Package) 74 Lau, ECTC- 2015-PDC WLSiP (Wafer-Level System-in-Package) Conventional SiP WLSiP  Basically, WLSiP use the fan-out wafer/panel-level packaging to build the SiP.  WLSiP pick up the known-good dies (KGDs) and discrete and place them on a temporary carrier and then over mold the whole reconfigured wafer with epoxy molding compound (EMC).  Remove the carrier and build the RDLs and mount the solder balls.  Finally, dice the molded wafer with RDLs and solder balls into individual units. There are many advantages of the WLSiP over th e SiP. One of the biggest advantages is lower profile and lower cost by eliminating the organic substrate! CHIP A CHIP B 75 Lau, ECTC- 2015-PDC PLSiP (Panel-Level System-in-Package) 76 Lau, ECTC- 2015-PDC PLSiP (Panel-Level System-in-Package) WLSiP PLSiP Higher throughput! 77 Lau, ECTC- 2015-PDC Package-Free LED (Embedded Wafer-Level LED CSP) 78 Lau, ECTC- 2015-PDC Package-Free LED (Embedded LED CSP) 79 Lau, ECTC- 2015-PDC SUMMARY AND RECOMMENDATIONS  Out of the three methods in forming the FOWLP, chip-first with die-down is the most simple and low cost while chip-last (RDL-first) is the most complex and high cost. Chip-first with die-up requires slightly more process steps (and thus is slightly costly) than chip-first with die-down.  Chip-first FOWLP can perform more than what fan-in wafer-level packaging (WLP) can do. However, some of the things that PBGA (plastic ball grid array) package can do, but chip-first FOWLP cannot are: (1) larger die size ( ≥12mm x 12mm) and (2) larger package size (≥25mm x 25mm). This is due to the thermal expansion mismatch and warpage limitations of the chip-first FOWLP. In this case, chip-last (RDL-first) FOWLP can extend the application boundary to die size with the range of ≤15mm x 15mm and fan-out package size (≤32mm x 32mm). With the heat spreader wafer option, the boundary can even be stretched to die size of <20mm x 20mm and fanout package size of <42mm x 42mm.  Chip-first FOWLP is just right for packaging semiconductor ICs such as baseband, RF/analog, PMIC, AP, low-end ASIC, CPUs (central processing units) and GPUs (graphics processing units) for portable, mobile, and wearable products. While chiplast (RDL-first) FOWLP is suitable for packaging the very high density and performance IC devices such as high-end CPUs, GPUs, ASIC, and FPGA (field programmable grid array) for high-end servers, computer, networking, and telecommunication products. 80 Lau, et al., CSR 20(3), 2016 SUMMARY AND RECOMMENDATIONS  Out of the three methods for fabricating the RDLs, PCB technology with LDI is the cheapest, while Cu damascene is the most expensive. The method used will depend on the Cu line w idth/spacing and thickness of the RDLs. Usually, if the line width/spacing and thickness are <5µm and ≤2µm respectively, then Cu damascene is the preferred option; if they are ≥5µm and ≥3µm, then use polymer with ECD; and for >10µm and ≥5µm, PCB with LDI should be used.  For chip-first FOWLP, the choice of reconfigured wafer or panel depends on the Cu line width/spacing of RDLs. If it is >10µm, then use large (610mm x 457mm) panel, and combine with PCB/LDI and SMT P&P to increase throughput and t o save cost. As to panel for fine line width/spacing, the industry need astandard on panel size.  For chip-first FOWLP, the curing temperature of polymers for RDL’s dielectric layer should be less than the critical temperature (230oC) of the compression molded EMC.  For chip-first FOWLP, the curing temperature of the EMC must be lower than the release temperature of the 2-side tape. For chip-first and chip-last FOWLP, high filler content EMC will shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage. Uniform filler distribution and filler size of the EMC will reduce flow marks/fill and enhance flowability.  WLSiP is a cost-effective way to build low-profile and low-cost SiPs. PLSiP can increase throughput.  Embedded Wafer-level packaging is a low-cost and high throughput solution for 81 Lau, et al., CSR 20(3), 2016 acka e-free LED CS Ps . Flip Chip Assembly 82 Flip Chip Assemblies HH HH HHHHH H (a) Mass Reflow of C4 or C2 B umps (CUF) fff HH HH HHHHH H (b) TCB with Low-Force of C2 Bumps (CUF) HH FFF HH HHHHH H (c) TCB with High-Force of C2 Bumps (NCP) HH FFF HH 83 (d) TCB with High-Force of C2 Bumps (NCF) Lau, ECTC-PDC-2014 (a) Mass Reflow of C4 or C2 Bumps (CUF) LPDDR4 Wirebonds Coreless Package Substrate for LPDDR4 A9 2-2-2 Package Substrate for A9 processor A9 application processor fabricated by 14/16nm Fin-FET process technology 150µm pitch staggered C4 bumps 0.4mm pitch solder balls LPDDR4 2-chip cross-stack Wirebonds 3-Layer Coreless substrate A9 90µm Solder balls .35mm pitch 2-2-2 build-up substrate (380µm thick and 75µm hole) PCB 84 Lau, ECTC-PDC-2016 (b) TCB with Low-Force of C2 Bumps (CUF) Chip Substrate Chip Cu-Pillar Solder Cu Pad Organic Substrate 85 Intel/ASM ECTC2015 (c) TCB with High-Force of C2 Bumps (NCP) Coreless substrate Upper substrate 1-2-1 buildup substrate 408 Cu-core balls 994 Solder balls Snapdragon 805 Processor: 10.9mm x 11mm x 95µm CuSnAg bumps @110µm pitch 30µm bump-height after TC-NCP PCB TC-NCP Solder 86 Lau, ECTC-PDC-2015 3D IC Integration 87 CONTENTS  Memory chip stacking  Wide I/O DRAM, Wide I/O2, or Hybrid Memory Cube (HMC)  High Bandwidth Memory (HBM)  3D CIS/IC Integration  3D MEMS/IC Integration  3D Hybrid Integration 88 Memory Chip Stacking with TSV for capacity and lowmemory power consumption (not for wide bandwidth). 89 Samsung Mass-Produces Industry's First TSV-based DDR4 DRAM Server Farm 78 TSVs for each DRAM! This is not a wide I/O device, nor does it contain a base logic die. It is just for memory capacity and low power consumption. Microbumps On November 26, 2015, Samsung start to produce the 128GB RDIMM (dual inline memory module) TSVs DRAMs 90 Lau, ECTC-2015-PDC High Bandwidth Memory (HBM) Memory Chip Stacking with TSV for memory capacity, low power consumption, and wide bandwidth. 91 High Bandwidth Memory (HBM) DRAM (Mainly for Graphic applications) JEDEC Standard (JESD235), October 2013 HBM is designed to support bandwidth from 128GB/s to 256GB/s Hynix’s HMC HBM DRAM TSV/RDL Interposer TSV Optional Base Chip GPU/CPU/SoC HBM Interface Organic Package Substrate PCBPCB Underfill is needed between the interposer and the organic substrate. Also, underfill is needed between the interposer and the GPU/CPU and the memory cube 92 Lau, ECTC-2015-PDC AMD’s GPU ( Fiji), Hynix’s HBM, and UMC’s Interposer The GPU (23mm x 27mm) is fabricated by TSMC's 28nm Process technology M B H M B H M B H GPU B M H Stiffener Ring The Organic Substrate (54mm x 55mm) is with 2111 balls at 1.2mm pitch The Si-interposer (28mm x 35mm) is fabricated by UMC’s 65nm process 93 technology Lau, ECTC-PDC-2016 AMD’s graph card made by Hynix’s HBM, which is TCB of the NCF DRAM chips one by one Microbump GPU with microbumps HBM Cu HBM Solder V S T C4 GPU HBM TSV-Interposer Build-up organic substrate HBM TSV-Interposer 1st DRAM 2nd DRAM 3rd DRAM 4th DRAM TSV-Interposer Cu Cu C4 PTH 4-2-4 Build-up substrate 94 Lau, ECTC-PDC-2016 Nvidia’s P100 with TSMC’s CoWoS and Samsung’s HBM2 HBM2 HBM2 GPU HBM2 HBM2 4DRAMs HBM2 GPU µbump Base logic die TSV Interposer (TSMC’s CoWoS) Package Substrate C4 bump 95 Lau, ECTC-PDC-2017 Solder Ball (d) TCB with High-Force of C2 Bumps (NCF) Base Film NCF Solder cap Cu Chip Wafer Chip solder cap Cu-pillar with NCF Lamination for wafer Cutting to wafer size and backgrinding Heat and Pressure Chip Cu Cu Blade NCF Cu-pillar with solder cap covered with NCF Solder Substrate Chip Chip Chip Removing based film and dicing the bumped wafer with NCF Chip Substrate 96 Lau, ECTC-PDC-2015 TCB with NCF (one chip at a time) Conventional Stepwise Process of Stacked Chips by Thermocompression Bonding (TCB) It takes about 10 sec to cure the NCF and at the same time melt a solder and connect to an electrode on the substrate. 97 Toray, Sept. 2015, IEEE/3DIC conference Toray’s Collective TCB of Stacked Chips : Bond-force = 30N; Temp. = 150oC Stage temperature = 80oC 1st step (3s): Bond-force = 50N Temp. = 220-260oC 2nd step (7s): Bond-force = 70N Temp. = 280oC 98 Peripheral portion AreaToray portion , Sept. 2015, IEEE/3DIC conference Hybrid Memory Cube (HMC) Memory Chip Stacking with TSV for memory capacity, low power consumption, and wide bandwidth. 99 Intel’s “Knight’s Landing” with 8 HMC Fabricated by Micron Stacked DRAMs Knight’s Landing have been shipping to Intel’s favorite customers since the 100 Lau, ECTC-PDC-2017 second-half of 2016. 3D CIS/IC Integration (SONY’s Hybrid Bonding) 101 SONY’s ISX014 3D IC Integration BI-CIS (2013) 102 CIS (insulator) wafer to logic (insulator) wafer bonding On chip color filter and micro lens BI-CIS Process Technology CIS (Si) W2W Bonding Surface CIS (Insulator) Logic (Insulator) Logic Process Technology Logic (Si) 50µm 103 SONY Cu-Cu Hybrid Bonding HVM SONY licensed Ziptronix’s ZiBond direct bonding in 2011 and Ziptronix’s direct bonding interconnect (DBI) in 2015. DBI is a hybrid bonding technology, which bonds the metal pads (usually Cu) and dielectric layer (usually SiO2) on both sides of the wafers at the same time. Now, SONY’d improved the hybrid DBI technology of w afers without wafer bumping, fluxing, flip chip assembly, cleaning, underfill dispensing and curing, and TSVs. SONY are the first one in the w orld to use Cu-Cu hybrid bonding in high-volume manufacturing (SONY IMX260 CIS for the Samsung Galaxy S7 shipped in 2016). 104 SONY’s (IMX260) Hybrid Bonding of the Back -side Illuminated CIS Chip on Processing Engine Chip. The Signals are coming out from the Processing Chip with wirebonds Processor Chip Processor Chip Wirebonds BI-CIS Chip BI-CIS Chip Wirebonds Microlens BI-CIS Chip SiO2-SiO2 Cu-Cu Processor Chip 105 3D MEMS/IC Integration Avago FBAR (Film Bulk Acoustic Resonator) 106 Wafer-scale Packaging for Avago FBAR (Film Bulk Acoustic Resonator)-based Oscillators Tx die Rx die TSV TSV is made by laser TSV TSV 107 Hermetic oscillator package containing (A) lid with integrated active circuitry and (B) FBAR die ICP TSV TSV TSV In the Avago microcap process, the FBAR is fabricated on one wafer while a second “lid” wafer contains through-wafer vias (TWV or TSV), Au pads, sealing structures, and a recessed air cavity above the FBAR TSV TSV TSV ICP (a) Cap Wafer Pad ICP Pad Pad Pad Pad Pad ICP (b) FBAR Wafer 108 Cross-section of FBAR/bipolar process showing completed die Au Pads V S T V S T IC Cap Wafer FBAR Circuit FBAR Wafer Au Au Pads TSV IC Cap Wafer FBAR Circuit FBAR Wafer 300µm 109 Embedded 3D Hybrid Integration 110 Integrated planar optical waveguide PCB Solder Bumps VCSEL Polymer Waveguide Photodiode FR-4 PCB Assembled OCEB using SMT 45º Mirror (end) formed by Excimer Laser Processing Measured eye-diagrams of the OECB. (a) 1.25Gb/s. (b) 2.5Gb/s 111 Embedded hybrid 3D integration for opto-electronic interconnects Heat Slug TIM Serializer or deserializer Solder Ball Driver chip VCSEL or TIA or PD TSV TIM Cu Heat Spreader Heat Slug Heat Slug Polymer Waveguide Mirror Optical layer support (film) Mirror Laminated Substrate/Board Special Underfills (e.g., Transparent) Buried via (filled or unfilled) for electrical interconnects Special Underfills (e.g., Transparent) VCSEL = Vertical Cavity Surface Emitted Laser (None transparent); PD = Photo Diode Detector (None transparent); TIA = Trans-Impedance Amplifier. 112 SUMMARY TSVs straight through the same DRAMs is the right way to: enlarge the memory capacity lower the power consumption increase the bandwidth lower the latency (enhance electrical performance) reduce the form factor Unfortunately, due to the high-cost in making the TSVs and stacking the DRAMs, currently, it is used only for high-end servers, graphics, networking, and computers. 113 2.5D IC Integration and TSV-Less Interposers 114 CONTENTS TSMC/Xilinx’s CoWoS Xilinx/SPIL’s TSV-less SLIT SPIL/Xilinx’s TSV-less NTI Amkor’s TSV-less SLIM Intel’s TSV-less EMIB ITRI’s TSV-less TSH Shinko’s TSV-less i-THOP Cisco’s TSV-less organic interposer Statschippac’s TSV-less FOFC-eWLB ASE’s TSV-less FOCoS Mediatek’s TSV-less RDLs by FOWLP Samsung’s TSV-Less organic interposer SONY’s TSV-Less CIS 115 Package Substrate for Flip Chips Chip 1 Underfill Chip 2 Build-up Package Substrate Not-to-scale PCB (a) Underfill Microbumps Chip 1 Chip 2 RDLs Underfill Underfill TSV TSV Interposer Chip 2 RDLs C4 Bumps Build-up Package Substrate Microbumps Chip 1 Build-up Layers Solder Balls PCB C4 C4 Bumps Build-up Package Substrate Build-up Layers Solder Balls PCB 116 (b) 2.5D IC integration (c) TSV-less interposer TSMC/Xilinx’s Chip on Wafer on Substrate (CoWoS) 117 Xilinx’s Passive Interposers with TSV and RDL for Wide I/O Interface in FPGA Products For better manufacturing yield (to save cost), a very large SoC has been sliced into 4 smaller chips (2011) (10,000+) With 4 RDLs 118 Xilinx/TSMC’s 2.5D IC Integration with FPGA Chip Chip Interposer C4 Bumps P T H Build-up Layers Core Devices Package Substrate Metal Layers Metal Contacts (Cannot see) Si Solder Balls Micro Bump Cu Pillar Solder 4RDLs Interposer The package substrate is at least (5-2-5) T S V RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 bumps on 45 m pitch Interposer is supporting >200,000 bumps 119 Xilinx/SPIL’s TSV-less SLIT (Silicon-Less Interconnect Technology) 120 Xilinx/TSMC’s CoWoS Devices (Cannot see) Metal Contacts Xilinx/SPIL’s SLIT Metal Layers Si Chip Cu Pillar Micro Bump Cu Pillar Solder Solder Si Chip Micro-bump 4RDLs 4RDLs C4 Interposer TSV and most interposer are eliminated! Only RDLs remained. T S V 65nm RDLs C4/Contact via C4 C4  No entire TSV fabrication module  Lower cost  Better performance  Lower profile  No thin wafer handling technology  No novel backside TSV Package Substrate Solder Ball revealing process  No multiple inspection & metrology steps for TSV fabrication & backside TSV revealing steps. 121 Xilinx/SPIL IMAPS Oct 2014 TSV-Less Interconnect Technology CHIP Cu-Pillar Solder Pad Solder RDL Passivation Si-wafer Si-wafer (a) RDLs and contact pad build-up on a Si-wafer CHIP Si-wafer (b) Chip to wafer bonding Molding Compound CHIP Si-wafer 122 (c) Underfilling (d) Over molding the whole wafer TSV-Less Interconnect Technology Reinforcement Wafer (Heat Spreader) Molding Compound CHIP CHIP (e) Reinforced wafer and Backgrind the Si-wafer (f) Passivation, photoresist, mask, litho, etch, sputter Ti/Cu, photoresist, mask, litho Reinforcement (Heat Spreader) CHIP Molding Compound CHIP Underfill Cu-Pillar Solder Pad RDL RDL C4 (g) Cu plating Passivation Ti/Cu UBM Cu Contact pad 123 (h) Strip photoresist, etch Ti/Cu, C4 bumping TSV-Less Interconnect Technology Reinforcement (Heat Spreader) Molding Compound CHIP Underfill Cu-Pillar Solder Solder Pad RDL RDL Passivation C4 UBM Contact pad Package Substrate Solder Ball PCB 124 Amkor’s TSV-less SLIM (Silicon-Less Integrated Module) 125 Amkor’s SLIM (Silicon-Less Integrated Module) S V T Interposer RDLs      Foundry BEOL layers retained Same CuP bond pads Same UBM and solder bump No TSV Much thinner 126 Amkor, 11th International Conference and Exhibition on Device Packaging, 2015. Intel’s TSV-less EMIB (Embedded Multi-Die Interconnect Bridge) 127 Embedded Multi-Die Interconnect Bridge (EMIB) – A High Density, High Bandwidth Packaging Interconnect Ravi Mahajan, Robert Sankman, Neha Patel, Dae-Woo Kim, Kemal Aygun, Zhiguo Qian, Yidnekachew Mekonnen, Islam Salama, Sujit Sharan, Deepti Iyengar, and Debendra Mallik Assembly Test Technology Development Intel Corporation Chandler, Arizona, USA [email protected] CHIP CHIP EMIB CHI CHI EMIB P P Organic Package Substrate PCB CHIP EMIB Microbumps Resin Film EMIB 128 Intel IEEE/ECTC2016 RDLs Contact Pads Cu-foil Drilling and Cu Plating Schematic showing the EMIB concept 129 Heterogeneous Integration using Intel’s EMIB and Altera’s FPGA Technology FPGA C4 bumps Microbumps Microbumps C4 bumps HBM RDL EMIB C4 bumps FPGA Package Substrate Microbumps HBM RDL EMIB Via Solder Ball PCB 130 Intel/Altera, November 2015 Intel/AMD/Hynix Heterogeneous Integration using Intel’s EMIB HBM EMIB HBM HBM EMIB EMIB Intel/CPU HBM RDL EMIB AMD/GPU EMIB EMIB HBM HBM Microbumps C4 bumps IB M E C4 bumps GPU CPU EMIB Package Substrate EMIB Hynix HBM Organic Package Substrate Microbumps HBM RDL EMIB Via Solder Ball PCB http://www.digitimes.com.tw/tw/dt/n/shwnws.asp?CnlID=1&Cat=10&id=493987&query=%A6%B3%A4F%AD%5E%AFS%BA%B8%A5%5B%AB%F9%A 131 1A%B6W%B7L%B1N%B1o%A8%EC%A7%F3%A4j%AA%BA%A7U%A4O%B9%EF%A7%DCNVIDIA (2/20/2017) ITRI’s TSV-less TSH (Through-Silicon Hole) 132 A TSH interposer supporting chips with Cu pillars on its topside and chips with solder bumps on its bottom-side Through-Si Holes (TSH) Interposer chip Micro Solder joints RDL RDL Solder RDL bump chip Non-metallization holes on the TSH interposer RDL RDL chip Cu wire or pillar RDL chip Solder bump Organic Package Substrate Solder ball Solder ball Printed Circuit Board Not-to-Scale Underfill is needed between the TSH interposer and package substrate. Underfill may be needed between the TSH interposer and chips. 133 Lau et al., IEEE/CPMT Transactions, 2014 SEM images of the Cu UBM/pads and Cu pillars (diameter = 50μm at the bottom and = 45μm at the top) Si 9μm 50μm Cu Pad/UBM 45μm Cu Top-view of Cu Sipillars with Photoresist Center =319 Radius = 22.5μm Length =141.6μm Area = 1594.7μm2 Photoresist Add Company Logo Here Lau et al., IEEE/CPMT Add Author’s Name HereTransactions, 2014 May 27 – 30, 2014 134 TSV-Less Interposer – TSH Interposer Non-metallization holes on the TSH interposer Solder bumps between TSH Interposer and package substrate Cu Pillar Top Chip Bottom Chip Package Substrate Solder bumps between TSH Interposer and Top- Chip and PCB Bottom-Chip TSH Interposer Underfill Holes in the TSH Interposer Top Chip Cu-Pillars Package Substrate PCB 135 (a) Lau et al., IEEE/CPMT Transactions, 2014 (b) Shinko’s TSV-less i-THOP (Integrated Thin film High density Organic Package) 136 Development of Organic Multi Chip Package for High Performance Application N. Shimizu, W. Kaneda, H. Arisaka, M. Koizumi, S. Sunohara, A. Rokugawa, and T. Koyama Shinko Electric Industries Co., Ltd. 36 Kita Owaribe Nagano-shi, 381-0014, Japan 81-26263-4585, no [email protected] IMAPS2013 and ECTC2014 137 Shinko’s 2.5D IC Integration without TSVs Chip-to-chip interconnection through 2µm width traces Chip Chip 40µm-pitch Pads Thin Film (2 layers + FC Pad) Conventional Build-up Substrate (1-2-2) Chip2 Chip1 Chip1 Chip2 2µm line width/spacing (C2C connection) Chip1 Chip2 138 Shinko, ECTC 2014 Cisco/eSilicon’s TSVinterposer -less organic 139 3D SiP with Organic Interposer for ASIC and Memory Integration Li Li, Pi erre Chia, Paul Ton, Mohan Nagar, Sada Patil, Jie Xue Cisco Systems, Inc. San Jose, CA 95134, U.S.A. e-mail: [email protected] Javier DeLaCruz, Marius Voicu, Jack Hellings, Bill Isaacson, Mark Coor, Ross Havens eSilicon Corporation San Jose, CA 95002, U.S.A. 140 IEEE/ECTC2016 A schematic cross-sectional view of the 3D SiP designed HBM_Functional HBM_Mechanical Cu Micro-Pillar Organic Interposer C4 Bumps HBM ASIC (FPGA) HBM_M ASIC (FPGA) Organic Interposer 1-2-1 Package Substrate 141 ASE’s TSV-less FOCoS (Fan-Out Chip on Substrate) 142 Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate (FOCoS) Yuan-Ting Lin, Wei-Hong Lai, Chin-Li Kao, Jian-Wen Lou,Ping-Feng Yang, Chi-Yu Wang, and Chueh-An Hseih* Advanced Semiconductor Engineering (ASE), Inc. Kaohsiung, Taiwan (ROC) e-mail: [email protected] CoWoS Die1 Die2 ASE’s FOCoS EMC Microbumps + Underfill EMC Die1 TSV-interposer + RDLs Die2 RDLs Package Substrate Package Substrate Solder Balls Solder Balls C4 bumps RDLs UBM C4 bump ASE IEEE/ECTC2016 RDLs RDLs C4 bumps MediaTek’s TSV-less RDLs by FOWLP 144 A Novel System in Package with Fan -out WLP for high speed SERDES application Nan-Cheng Chen, Tung-Hsien Hsieh, Jimmy Jinn, Po -Hao Chang, Fandy Huang, JW Xiao, Alan Chou, Benson Lin Mediatek Inc Hsin-Chu City, Taiwan 145 Mediatek IEEE/ECTC2016 FOWLP carrier structure Si Die EMC Pad DL1 RDL1 DL2 RDL2 DL3 RDL3 DL4 Cu µbump Solder cap Package Substrate RDL3 DL4 UBM Cu-pillar µbump µbump Solder cap Solder resist opening Cu pad Package substrate 146 Trends in 2.5D IC Integration (Interposers) Chip 1 Chip 2 Package Substrate PCB Underfill UBM Chip 1 Microbumps Chip 2 RDLs Underfill TSV Interposer TSV UBM Solder Bumps Package Substrate Solder Balls Build-up Layers TSV-Less Interposers Xilinx/SPIL’s TSV-less SLIT SPIL/Xilinx’s TSV-less NTI Amkor’s TSV-less SLIM Intel’s TSV-less EMIB ITRI’s TSV-less TSH Shinko’s TSV-less i-THOP Cisco’s TSV-less organic inter. Statschippac’s TSV-less FOFC-eWLB ASE’s TSV-less FOCoS Mediatek’s TSV-less inter. Samsung’s TSV-less organic inter. Still keep the RDLs mainly for lateral communication between chips PCB 147 Thank you very much for your attention! 148