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Fabrication Of Semiconductor

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SEMICONDUCTOR FAB PROCEDURE The story of the Chip The design process VLSI DESIGN  – Specifications Specifications..  – Design hierarchy.  – Design abstraction - HDL / schematic.  – Design simulation - subckts / complete  – Design verification.  – Design synthesis / custom Transistor level.  – Design layout - EDA tools for layers.  – DRC / LVS verification .  – GDSII tape out. EDA TOOL CENTRIC SILICON MATERIAL INDUSTRY  – Source of polished silicon wafers as substrates   s   s    l   e   e   l    d   u   o   R    M   g  ,    i   n   s   r   e    i   e   r   y   a   a   r    L    b    i    L   &   s    l    i   a    t   e    d   r   e   y   a    L    I    I    S    D    G The VLSI Fabrication Foundary   y   a   r   r    A    d   e   g   a    k   c   a    P The VLSI fab process  Packaging  The packaged chip The ASIC  The programmable ASIC  Program codes FPGA / CPLD A.00 1 [email protected] SEMICONDUCTOR FAB PROCEDURE  Poly Crystalline  Silicon Crystal Pulling  Wafer   Epitaxy  Process Wafer slicing   Lapping  &  Polishing  Oxidation & Layering   Photoresist coating   Pattern  preperation  Stepper exposure  Acid   Etch  Ashing   Metal   Etch  Develop &  Bake  Spin  Rinse  Dry  Metal   Deposition  New Copper   Deposition Wire  Bonding  CVD  Process  Probe test  & Die cut   Ion  Implant   Packaging  A.00 2 [email protected] SEMICONDUCTOR FAB PROCEDURE Raw Polycrystalline silicon is manufactured by mixing refined Tri-chlorosilane with Hydrogen gas in a reaction furnace and allowing the polycrystalline silicon to grow onthe surface of electrically heated tantalum metal wicks.  Poly Crystalline  Silicon  Raw Poly-crystalline  Silicon Rods  Poly silicon ingots / nuggets They then refine the polycrystalline tubes by dissolving in hydrofluoric acid and produce poly sili con ingots. Because polycrystalline silicon has randomly oriented crystalline structure it does not haveconsistent  properties for fabrication of semiconductor devices like transistors. Polycrystalline silicon has to be converted into Single Crystal Silicon by a process called Czokralski Crystal Growing or Crystal pulling into single crystal of known crystal orientation and without defects and having a given electrical property by addition of controlled dopants to achieve n-type or p-type single crystal silicon ingots. Usually polycrytalline silicon is basically intrinsic in nature with a high resistivity.Commercial companies which produce Polysilicon include MEMC , KOMATSU, Shin-Etsu & WACKER SILTRONICS. The next step in the Semiconductor manufacturing process is converting Polysilicon into Single crystal silicon and with a controlled dopant to form either a n-type or p-type silicon crystal of given orientation and resistivity. This is a very crucial step in the  processing of silicon for the semiconductor industry, since without single crystal silicon it is not possible to build any integrated circuit . Polysilicon itself cannot be used since its crystal structure is non-uniform . This process of single crystal formation is called Crystal Growing. Crystal Pulling  Crushed polysilicon crystalline is doped with a controlled amount of arsenic or   phosphorous for n-type or boron for p-type and melted at about 1400 deg., Centigrade in a Quartz cruicible surrounded by an inert gas atmosphere of high purity argon. The melt temperature is very precisely cooled to a given temperature and a seed of a given crystal orientation is dipped and slowly rotated as it is pulled upwards at a controlled speed. Surface tension causes a little of the liquid silicon to rise with the seed and cool to form a single crystal as the same orientation as the seed. The process is carefully controlled and continued with the pulling speed varied to change the diameter of the crystal being grown and then controlled to maintain the given diameter as the process continues. The entire process is very slow and may take several days to complete when the finished crystal grown is about 100 Kgs in weight and 12 inches in diameter. A.00 3 [email protected] SEMICONDUCTOR FAB PROCEDURE Single crystal Silicon ingots are characterised by their crystal orientation and n-type / p-type electrical resistivity. The crystal orientation itself is identified using X-ray diffraction and grinding one or two flats of the surface of the crystal. This is done before the crystals are sliced into wafers. Secondary Flat  Silicon Crystal Characterization Primary flat Once the Silicon crystal ingots are characterized they have to be sliced into wafers about 500 microns thick . This process is done in a precision machine called the ID saw with a diamond studded blade whose thickness is about 300 microns. The blade is made rigid on the IDsaw machine using special hydraulics and the diamond studded inner periphery is used as the cutting edge. The Wafers at this stage are called “as cut wafers”. Saw marks will be present and these need to be removed. The wafers need to be sliced without bow .   ID Wafer Slicing  The as cut wafers are lapped mechanically in a counter-rotating lapping machine with aluminium oxide as the lapping medium in the form of fine slurry. This process mechanically removes the slicing  blade marks and makes the two surface sides of the wafer flat and  parallel to each other. This process is crucial since further IC manufacturing process relies on this flatness of the wafer surface where the devices are fabricated after polishing. This process cannot correct bow which needs to be taken care in the slicing stage . Wafer Lapping  The lapped wafers are etched in an acid medium using a mixture of nitric / acetic or Sodium Hydroxide to remove any microscopic damages left over   by the mechanical lapping process. The wafers are then cleaned thoroughly with ultra-purified RO / DI water to remove any trace of the etching chemicals. Since the technology feature size of the devices that will ultimately be fabricated is deep in the sub micron range, extremely tight control on the nature of the cleansing DI water is essential for the success of the process. Wafer Polishing  The wafers are then polished in a series of a combination of chemical and mechanical polishing. The wafers are held in a hard ceramic chuck using a wax to hold one side of the wafer and the polishing is carried out on the other side. For the process of IC manufacture only one side is polished and the devices are made on this polished side at a later stage. The polishing medium is a slurry of  fine silica powder in DI/RO water and Sodium hydroxide. The process is carried out in two or three steps with finer and finer slurry to achieve high polished quality. The polished wafers are cleaned in a mult-step process with ammonia, hydrogen peroxide, and RO/DI water. An Hydrofluoric acid rinse removes natural oxides and metallic impurities which would be detrimental to further   process stages. The polished wafers are completely handled in ultra-clean rooms A.00 4 [email protected] SEMICONDUCTOR FAB PROCEDURE  Epitaxy Process The polished wafer enters the device fabrication stage . Many times the devices are not made directly on the polished surface of the silicon wafer itself, but on a epitaxial layer of silicon grown on the polished side of the wafer which is now called a substrate. This process called EPI grows a layer of single crystal silicon from vapour into the single crystal silicon substrate at high temperatures. Trichlorsilane or Silicon tetrachloride and hydrogen are combined with either  diborane or phosphine gas to achieve the type resistivity ( p-type or n-type respectively). The purpose of the epi layer is to create a different layer of  controlled conditions other than the substrate’s polished layer itself. The epi layer grows following the crystal orientation of the silicon substrate. Typical EPI Reactor  The fabrication process enters the device manufacture steps now. The first step in this process and the backbone to the fabrication line is the Oxidation Process. This process produces a thin layer of Silicon dioxide on the substrate / or on the epi layer as the case may be by exposing the wafer to a mixture of high-purity oxygen and hydrogen at +/- 1000 deg C. This oxide layer forms the insulating layer and may  be up to about 1500 angstroms. Oxides are also used for gate in the MOS device and in this case the thickness is about 200 to 300 angstroms. A.00 5 Oxidation & Layering  [email protected] SEMICONDUCTOR FAB PROCEDURE Photoresist is a photo-sensitive material applied on the wafer in a liquid state in small quantities. The wafer is then spun at about 3000 rpm which spreads this photo-resist liquid layer into an uniform layer between 20 to 100 microns thick.. The photo-resist layer is then exposed to light of a specific wavelength with the MASK superimposing the layer details for photoresist to be removed from specific locations.  Photo Resist Coating   Mask Making  The MASK itself carries the layer image to the details worked out by the IC designer for the layer under  fabrication. The Fabrication process itself is thus an incremental process forming layer after layer of the various layers in the design in a given sequence to implement physically all the devices and the metallic interconnects to form the complete IC. The pattern for each layer is in the form of a Software code designed  by the IC design team. The Reticle for the layer in consideration is made in the Pattern Generator which rasterizes the CAD pattern and with a series of beam splitters and mirror / shutter combinations patterns the reticle’s surface as a one-to-one image of the CAD layer. For devices larger than 1.5 microns, the reticle is for the entire wafer, but for smaller devices, the patter corresponds to only one device (one of the many on the wafer) and stepped individually.Semiconductor devices are made up of as many as 50 individual layers of silicon,poly-Silicon , Silicon Dioxide, Metals and Silicides. The pattern of each layer is contained on a MASK called a RETICLE. These are 1 to 10 times the actual size of the patterns of each layer and a group of these make up all the needed layers of a typical device and this group is called a SERIES. A RETICLE is an optically clear Quartz Substrate with a chrome pattern. To keep the surface of the Reticle clean, a thin  plastic sheet called the PELLICLE is mounted a short distance away from the surface of the reticle. This allows the reticle surface to be cleaned without contacting the Chrome mask surface, and also ensures that any microscopic dust which may settle on the Reticle will be out of focus during exposure and will not create defective layer.   Rotating polygonal    scanning mirror  Scan  Lens Source electrodes Steering   Mirror  Thermal field emission electron beam source Source condensing lens  Auxiliary blanker  & limiting aperature  Magnification adjustment   Rasterizer   Pattern description data  Acousto - optic modulator   Brush of  32 beams  First transfer lens Second transfer lens  Pattern generating  blank & aperture Three stage beam deflection system 32 beam  splitter  Objective lens Objective  Lens  Laser mask height sensor   Beam shaping  Charge Amp Ultra-violet   Laser   Laser interferometer   for stage position control   Mask   XDY stage  Laser Pattern generator - scheme  E-beam pattern generator  A.00 6 [email protected] SEMICONDUCTOR FAB PROCEDURE  Stepper Exposure Applying and exposing photoresist to create a desired layer on a wafer  is similar to MASK making. A stepper Machine is normally used for  this purpose. In this process a photoresist coated wafer is exposed to a single wavelength of UV light passing through a Reticle which contains the image of a given single layer of the device under  fabrication. The term “Stepper” comes from the “Step and Repeat” action of moving the wafer in the X and Y axes to align the Reticle with each individual device position for all the devices that are eventually going to be implemented on the wafer  UV light is used because modern device features are very small and are comparable to the wavelength which ultimately becomes the limiting factor. UV has a shorter wavelength (less than 500 nm) than visible light which allows the creation of small features. Even  broadband UV (or multi-wavelength) is capable of going down to 2 microns and hence useless for modern day devices having feature size near 0.18 microns. This requires use of 436 nm (G-line), 405 nm (H line ) , 965 nm (I-line) and 248 nm (Deep UV). Experimentations are also in progress with X-rays for even shorter  wavelength. The Stepper Machine has got elaborate control systems and technologies for  accurate geometric movement control and internal temperature control to prevent any thermal expansion / contraction from ruining the accurate dimensional control needed in the  process. This process of lithography is one of the most complex and advanced steps in IC fab techniques since the process creates a preferred window where further processes layers are going to  preferentially fit. Any error here compared to the geometry feature size of the technology will result in catastrophic failure of the entire fab  process After exposure the wafers are developed in either an acid or base solution to remove the exposed portion of the Photoresist. The wafer is then soft baked at a low temperature to harden the remaining areas of the photoresist.  Develop & Bake  After developing and stripping  A.00 7 [email protected] SEMICONDUCTOR FAB PROCEDURE  Acid Etch Removing selected areas of material from the wafer involves the use of  different types of acids , bases or caustic solutions. Much of the etching work is carried out in specially designed automatic wafer handling benches. For  example to remove oxide layer without damaging the underlying silicon or   polysilicon layer, phosporic acid is used for etching silicon nitride layers, nitric acid for etching metal layers and sulphuric acid used to remove photoresist. Another highly corrosive acid that is used in this processing step is HF (Hydro Floric acid ). Acid etching procedures are generally need for cleaning the surface as well as removal of the mechanical fractures that could have been created in the previous process handling steps. Sometimes these steps are referred to as chemical milling in the micro fabrication industry. Protection of the wafer surface from damage and contamination are the primary concerns in a wafer fabrication facility. Silicon is extremely brittle and so handling of wafers is carried out using the wafer holding cassettes or boats and adequate measures taken to  prevent even the smallest dust particle from coming into contact with the wafer surface which will damage the device fabrication process. Fabrication facilities are housed in multimillion dollar Cleanrooms and all personnel wear special gowning (”bunny” suits and surgical masks and gloves) to reduce the possibility of air-borne contamination. Robotics and automated wafer handling is e mployed wherever possible, and when manual handling is needed, vaccum wands are used to handle wafers. Even with these precautions wafers have to be constantly cleaned and for this purpose the SPIN,RINSE and DRYER is used. For the purpose of cleaning RO/DI water is used and Ultra High Purity Nitrogen is used for Drying.  Ion Implantation  Spin & rinse - drying  Ion implant creates an exclusively doped layer in the substrate. Device fabrication needs precise areas of the substrate doped in precise methods to form various parts of the devices. The Ion implanter does exactly this. The ion implanter uses a high current accelerator tube and steering and focus magnets to bombard the wafer surface with ions of a  particular dopant which get implanted in the wafer surface. To create an insulating or p-type region and acceptor ion such as boron, gallium or  indium is implanted. To create a conducting or n-type region a donor  ion such as antimony, arsenic , phosphorous or bismuth is implanted. The bombarding ion-density is actually controlled by the ion-beam current ( normal order in the milli-amps range). The process  parameters for ion-generation and focus is precision controlled without which mis-alignment will ruin the devices under fabrication.  Inside the implanter  A.00 8 [email protected] SEMICONDUCTOR FAB PROCEDURE Metals like aluminium, gold and tungsten are used to create conductive layers on the device. They are generally applied with two different methods, evaporation and sputtering, grouped into category of “Physical Vapour Deposition” or  PVD.  Metal deposition Evaporation uses heat (either an electric filament or an electron beam) and high vaccum to vaporize the metal source. The vacuum is of the order of 1 to 5 micro Torr. The evaporating source material condenses on the cool wafer  surface held in a planetary or semi-hemispherical arrangement over the source. Sputtering uses a cathode to create an argon plasma which  bombards the source material. The dislodged metal molecules are focused by a “lens” of radiation-absorbment material called the collimator and gets deposited in a thin film on the wafer surface. While the usual conductive layer metals are aluminium, gold and tungsten, the semiconductor industry has always been in search for a process to use Copper since the resistance of copper is 40 % less than aluminium which translates into about 15 % increase in speed. In ultra-small chips at high current densities, copper is far less vulnerable than aluminium to electromigration (movement of individual atoms caused  by high electric currents}causing voids and conductor breakdown. The problem with Copper was because it was considered as a Semi-conductor killer. Copper rapidly diffuses into silicon and also change the electrical properties of silicon in such a way as to prevent transistors functioning. However, IBM finally overcame this problem with a key technology for copper patterning called Damascene. In conventional deposition, a layer of metal and photoresist are deposited on the wafer . The unwanted metal is then etched away with an appropriate chemical, leaving behind the desired pattern. Next the spaces between the metallic wires so formed is filled with Silicondioxide and finally the entire wafer surface is polished to remove the excess insulator oxide. The Damascene process patterning involves the same steps, but reverses the order of  deposition. The patterns of the metal lines and vias is first formed in the oxide layer by etching the oxide. The metal is then formed on top of this and the excess metal thickness over and above the oxide thickness is  polished away. In both conventional and the Damascene patterning the process is repeated many times to form the alternating layers of metal wires and vias which form the interconnecting network on the chip. To overcome copper’s tendency to diffuse into silicon, IBM devised a means of depositing a complex copper structure on polymide, a compound used as an electrical insulator in silicon chips.  SEM view of the copper interconnect technology A.00 9 [email protected] SEMICONDUCTOR FAB PROCEDURE Chemical Vapour Deposition or CVD is a broad class of processes using controlled chemical reactions to create layers on the wafer surface. Prior to deposition the wafer is usually cleaned with a Dry Plasma etch  process using either Sulphur Hexafluoride or a combination of  tetrafluoromethane and oxygen. Special hybrids of Silicon and metal called Silicides can be used to create conductive layers. For example Tungsten Hexafluoride can be used for forming Tungsten Silicide layer. A Variant of the CVD process called Plasma- enhanced CVD or PECVD process uses a gas plasma to lower the temperature to obtain chemical reaction and achieve film deposition. Cleaning the CVD Chemical Vapour Deposition chambers is usually done with Nitrogen trifluoride plasma. The CVD tools illustrated are special kind of multichamber CVD tool called ‘The Cluster’ that can perform multiple sequential operations automatically.  Metal Etch Metal etch selectively removes portions of an aluminium layer to leave conductive circuit paths on a device. The process must precisely eliminate the metal left exposed by the photoresist pattern and avoid undercutting the sides of the remaining circuits. A wafer is placed into the etching chamber and given negative electric charge. The chamber is heated to 200 degree F and  brought to a vacuum of 10 milli torr, then filled with a positively charged  plasma (usually a mix of nitrogen, chlorine and boron trichloride). The opposing electrical charges cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a microscopic chemical and  physical ‘sand blasting’ action which removes the exposed Aluminium. Modern processes use a method called dry etch which is a plasma version of the acid etch. In this  process the etchant in gaseous form is created in a cold plasma environment under specific vacuum conditions. Since plasma is an ionic state, the ionised  particles etch the surface similar to chemical etching.  A Dry Plasma Etching fixture Once a silicon, metal or silicide layer has been created, the remaining photoresist is removed. This is done with a procedure called ashing, where a high temperature  plasma is used to selectively remove photoresist without damaging device layers.  Ashing  A.00 10 [email protected] SEMICONDUCTOR FAB PROCEDURE  Probe & Die test  After the final passivation layers are applied, the entire wafer goes through backside preparation, which thins the wafer to allow better heat dissipation and removes stress fractures which could cause breakage. Each finished wafer may contain several hundred actual devices or DIE. Automated methods to test and isolate faulty DIEs are carried out and the good devices scribed and cut-out into chips. A probe tester uses needle-like ‘probes’ to contact the bonding pads on each device and check its operation. Devices that fail are marked out. The cut DIEs are sent for the wire-bonding process. The yield of the process is the ratio of  the good devices in relation to the total devices targeted in the wafer. Wire bonding  Once seperated into individual DIE, the functional devices are attached to a LEADFRAME assembly and gold leads are attached via thermal compression or ultrasonic welding. The automated process attaches ultra-thin wires (about 30 microns ) between each device’s bonding pad and a connector of the Lead Frame. The wire bonding head   Packaging   Dip package After wire-bonding is completed, the packaging is completed  by sealing the device into a ceramic or plastic enclosure. A.00 11 The QUAD Package [email protected] SEMICONDUCTOR FAB PROCEDURE THE SEQUENCE  A.00 12 [email protected]