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ARCHITECTURE OF TMS320C54XX DIGITAL SIGNAL PROCESSORS

TMS320C54X INTERNAL BLOCK DIAGRAM

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ARCHITECTURE • Architecture of the TMS320C54XX comprises of:  CPU  Memory  ON-chip peripherals • This DSP uses modified Harvard Architecture • Provides a high degree parallelism due to separate program and data spaces which allows simultaneous access to program instructions and data.1. • They have 1 program and 3 data memory spaces .

select and store unit(CSSU)  Data address generation unit(DAGEN)  Program address generation unit(PAGEN) . CPU • Contains:  40-bit ALU  Two 40-bit accumulators  Barrel shifter  17× 17-bit multiplier  40-bit adder  Compare.1.

Also function as 2 separate 16-bit ALUs and perform two 16-bit operations simultaneously.1 ARITHMETIC LOGIC UNIT(ALU) ALU performs 2’s complement arithmetic operations and bit level Boolean operations on 16-. .1. and 40-bit words. 32-.

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• Accumulator divides into: – Guard bits(bits 39-32) – High-order word(bits 31-16) – Low-order word(bits 15-0) .B store output from the ALU or the multiplier/adder block.1.2 ACCUMULATORS • Accumulators A. • Either of the accumulators can be used as temporary storage for the other. • They also provide second input to ALU and accumulator A can be an input to the multiplier block.

1. • It has a 40-bit input connected to the accumulators or to data memory (using CB or DB) and a 40-bit output connected to the ALU or to data memory(using EB) • It produces a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. shift count field of status register ST1 or in the temporary register T. • The shift requirements are defined in the shift count field of the instruction.3 BARREL SHIFTER • It provides the capability to scale the data during an operand write or read. .

. Additional shift capabilities enable the processor to perform numerical scaling. The LSBs of the output are filled with 0s and the MSBs can either zero filled or sign extended. and overflow prevention operations. depending on the state of the sign-extension bit(SXM) in ST1.The barrel shifter and exponent encoder normalize the values in an accumulator in a single cycle. extended arithmetic. bit extraction.

4 MULTIPLIER/ADDER UNIT It performs 17× 17-bit 2scomplement multiplication with a 40-bit addition in a single cycle. Consists of several elements:  A multiplier  An adder  Signed/unsigned input control logic  Fractional control logic  A zero detector  A rounder(2s complement)  Overflow/saturation logic  A 16-bit temporary storage register(T) .1.

This function is used in determining the Euclidian distance and in implementing symmetrical and LMS filters which are required for complex algorithms . or Accumulator A  Selected from program memory. a data memory operand.Multiplier has 2 inputs:  Selected from T. correlation and filtering Multiplier + ALU together execute MAC computations & ALU operations in parallel in a single instruction cycle. data memory. Accumulator A or an intermediate value Fast on-chip multiplier allows convolution.

Performs:  maximum comparison between accumulator’s high and low word  allows both the test/control flag bit(TC) in the status register ST0 & the transition register(TRN) to keep their transition histories  Selects the larger word in the accumulator to store into the data memory .5 COMPARE.1. SELECT AND STORE UNIT(CSSU) CSSU accelerates Viterbitype Butterfly computations with optimized onchip hardware.

1. .6 DATA ADDRESS GENERATION UNIT DSP offers 7 basic data addressing modes:  Immediate addressing  Absolute addressing  Accumulator addressing  Direct addressing  Indirect addressing  Memory-mapped register addressing  Stack addressing During the execution of direct. the DAGEN computes the addresses of data-memory operands. indirect or memory mapped register addressing.

reset. PAGEN increments the PC as sequential instructions are fetched. which is referenced by the stack pointer(SP). single/multiple instruction repeats.1. calls. conditional operations. PAGEN may load the PC with a non-sequential value as a result of some instructions or other operations(branches. & interrupts) For calls & interrupts:  The current PC is saved onto stack. returns. the PC value in the stack is restored via return instruction .7 PROGRAM MEMORY ADDRESSING UNIT Program memory usually addressed with Program counter PC is loaded by PAGEN.  When interrupt service routine is finished.

2.bit buses(4program/data buses and 4 address buses) Program bus(PB). CAB.carries the instruction code & immediate operands from program memory Data buses CB & DB. EAB)-carry the addresses needed for the instruction execution DSP can generate up to 2 data-memory addresses per cycle using the 2 auxiliary register arithmetic units(ARAU0 ARAU1) – enables accessing 2 operands simultaneously . BUS STRUCTURE 8 major 16.carry the operands that are read from data memory Data bus EB. .carries the data to be written to memory 4 Address buses(PAB. DAB.

C54X DSP also has an on-chip bidirectional bus This bus is connected to DB & EB through a bus exchanger in the CPU interface.For accessing on-chip peripherals. .

INTERNAL MEMORY ORGANIZATION Memory organized into 3 individually selectable spaces:  Program  Data  I/O space DSP can contain RAM & ROM ROM:  Is part of program memory space & sometimes data memory space.  Contains a bootloader that is useful for booting to faster on-chip or external RAM RAM:  Dual-access type(DARAM)  Single-access type(SARAM)  Two-way shared RAM .3.

Can configure the DARAM & SARAM as data memory or program/ data memory.  The memory-mapped access provides a convenient way to save and restore the registers for context switches and to transfer information between the accumulators and the other registers.  .  DSP has 26 CPU registers+ peripheral registers that are mapped in data-memory space  Memory-Mapped Registers  Data memory space contains memory-mapped registers for the CPU and the on-chip peripherals.

ON-CHIP PERIPHERALS All the C54xE devices have a common CPU. but different on-chip peripherals  On-chip peripheral options:  1. 8-bit enhanced (HPI8). 8. 3. 10. General-purpose I/O pins Software-programmable wait-state generator Programmable bank-switching logic Clock generator Timer Direct memory access (DMA) controller Standard serial port Time-division multiplexed (TDM) serial port Buffered serial port (BSP) Multichannel buffered serial port (McBSP) Host-port interface (8-bit standard (HPI). 11. 5. 2. 6. 7. 9. 4. 16-bit enhanced (HPI16)) .

Memory-mapped register addressing modifies the memory-mapped registers without affecting either the current DP value or the current SP value. . Accumulator addressing-uses an accumulator to access a location in program memory as data. Stack addressing-manages adding and removing items from the system stack. Indirect addressing-uses the auxiliary registers to access memory. Direct addressing-uses seven bits of the instruction to encode an offset relative to DP or to SP. Absolute addressing-uses the instruction to encode a fixed address.ADDRESSING MODES Immediate addressing-uses the instruction to encode a fixed value. The offset plus DP or SP determine the actual address in data memory.