Transcript
SAP-1 Computer
Simple-As-Possible Computer Simple-As-Possible(SAP) Computer has been designed for beginners. be ginners. The main purpose of SAP is to introduce all the crucial ideas behind computer operation. There are three different generations of SAP. (SAP-1 SAP-2 SAP-3)
Simple-As-Possible Computer Simple-As-Possible(SAP) Computer has been designed for beginners. be ginners. The main purpose of SAP is to introduce all the crucial ideas behind computer operation. There are three different generations of SAP. (SAP-1 SAP-2 SAP-3)
SAP-1 Computer SAP-1 is a computer because it stores a program and data before calculations begin; then it automatically carries out the program instructions without human intervention. And yet, SAP-1 is a primitive primitive computing machine. machine. When compared to a modern computer, it is like a Neanderthal human compared to a modern person. SAP-1 is the first stage in the evolution toward modern computers.
SAP-1 ARCHITECTURE
SAP-1 Architecture Architecture is the conceptual design and fundamental operational structure of a computer system. It is the blueprint and blueprint and functional description of requirements and design implementations for various parts of a computer.
PROGRAM COUNTER
INPUT and MEMORY ADDRESS REGISTER 4
8
4
ACCUMULATOR 8 8
4
W Bus 8
ADDER SUBTRACTOR
4 8
RAM
RAM
8
8 8
B REGISTER
8 INSTRUCTION REGISTER 4 4
8
OUTPUT REGISTER 8
Controller Sequencer
BINARY DISPLAY
SAP-1 Architecture SAP-1 Architecture is a Bus-Organized Computer. All register outputs to W Bus are three-state; these allows orderly transfer of data. All other register outputs are two-state; these outputs continuously drive the boxes they are connected to.
Three-State DATA OUT
DATA IN
ENABLE 0 1 1
Din
Dout
X 0 1
OPEN 0 1
ENABLE
Din
Dout
= OPEN
0
Din
Dout
= CLOSED
1
Bus-Organized Computer
Bus is a group of wires that transmit a binary word. It is a common transmission path between the three-state registers.
LOAD A CLR
A REGISTER
ENABLE A
4
4
4
4
C REGISTER
LOADC CLR ENABLEC
BUS LOADB CLR ENABLEB
B REGISTER
4 4
4 4
D REGISTER
EXAMPLE OF BUS-ORGANIZED COMPUTER
LOADD CLR ENABLED
Data Transfers The advantage of bus organization is the ease of transferring a word from one register to another. To begin with, the same CLK signal drives all the registers, but nothing happens until you apply HIGH(1) signal to the control inputs(LOAD and ENABLE). In other words, as long as all LOAD and ENABLE inputs are LOW(0), the registers are isolated from the bus. CLR input clears the word in the register when HIGH(1).
EXAMPLE:
Transfer word 0101 from A to B. Then from B to C and from C to D. After all registers have the binary word, Clear all register
except D.
L A CLR E A
LC 0101 A
C
LB
LD
CLR EB
CLR EC
B
D
CLR ED
L A 1
CLR E A
1
LB CLR EB
LC 0101 A
C
CLR EC
LD 0101 B
D
CLR ED
Apply HIGH signal on E A and LC to transfer binary word from A to B.
L A CLR E A
LC 0101 A
0101 C
CLR EC
LB CLR 1
EB
LD 0101 B
D
CLR ED
Apply HIGH signal on EB and LC to transfer binary word from B to C.
1
L A CLR E A
LC 0101 A
0101 C
CLR EC
1
LD
1
LB CLR EB
0101 B
0101 D
CLR ED
Apply HIGH signal on EC and LD to transfer binary word from C to D.
L A 1
CLR E A
LC 0101 A
0101 C
LB 1
CLR EB
CLR EC
LD 0101 B
0101 D
Apply HIGH signal on CLR on A,B and C to clear its contents.
CLR ED
1
CP EP CLK
PROGRAM COUNTER
L A
8
4
ACCUMULATOR 8
CLR LM CLK
INPUT and MEMORY ADDRESS REGISTER 4
8 4
W Bus 8
ADDER SUBTRACTOR
E A CLK SU EU
4 8
CE
RAM
RAM
LI EI CLK
8
8 8
B REGISTER
8 INSTRUCTION REGISTER 4
CLR 4
8
OUTPUT REGISTER 8
Controller Sequencer C E L CE L E L E
S E LL
BINARY DISPLAY
LB CLK LO CLK
SAP-1 Architecture The SAP-1 Control unit consists of the Program counter, the Instruction Register and the Controller-Sequencer that produces the control word, the clear signals and the clock signal. The SAP-1 ALU(Arithmetic Logic unit) consists of an Accumulator, an Adder/Subtractor and a B Register. The SAP-1 Memory has the Memory Address Register and a 16x8 RAM. The SAP-1 I/O unit includes the programming switches, Output register and Binary display.
Program counter Program counter is a circuit counter that counts from 0000 to 1111. The binary word output of the counter (0000 to 1111) corresponds to the memory location or address(00H to 10H) of RAM where the instruction is written.
INPUT and Memory Address Register(MAR) INPUT is where the programming switches that allows you to send 4-bit address and 8bit data to the RAM. Memory Address Register(MAR) is part of the SAP-1 Memory. During a computer run, the output of the program counter(0000 to 1111) is latched into MAR. A moment later, MAR applies this 4-bit address to the RAM, where a read operation is performed.
Random-Access Memory(RAM) Before a computer run, the instruction or data word is stored in the RAM by using address and data switch registers. During a computer run, the RAM receives the 4-bit address from the MAR and a read operation is performed. In this way, the instruction or data word stored in the RAM is placed on the W bus for use in some other part of the computer.
To write data on the RAM: ----Address the memory where the data will be written. [SAP-1 uses two 16x4 TTL RAM. In this case, there are 16 memory locations(address) to write on with 4 bits of data.] ----Clear both CE and WE to perform write operation. Example: Write 1001 on 10H.
RAM CE
WE
0
D0
O0
D1 D2
O1 O2
D3
O3
A3
A2
A1
A0
1 0 0 1 1 0 1
----
AH
----
BH
1001
CH
0
To read data from the RAM: ----Address the memory where the data will be read. ----Clear CE and set WE to perform Read operation. Example: Read the data stored in 10H.
0 A0 – A3 Address bits D0 – D3 Data Input O0 – O3 Data Output (threestate) CE Chip Enable WE W it E bl
0
1 1 0 0 1
1 0 1
0
----
AH
----
BH
1001
CH
Instruction Register Instruction register is a part of control unit and a buffer register that fetch an instruction from the RAM when the computer does a memory read operation. The upper nibble(MSB) output of the instruction register goes directly to the Controller-Sequencer, the lower nibble(LSB) is a three-state output that is read onto the W bus when needed.
Controller-Sequencer This controls the whole operation of the computer(like a supervisor telling everyone what to do) by sending out 12-bit word called control word. The control word has the format of: CON = CPEPLMCE LIEIL AE A SUEULBLO Also, the controller-sequencer contains the Clock generator which sends out CLK and CLK signals and the Master reset which sends out CLR and CLR signals.
Accumulator Accumulator is a part of ALU and a buffer register that stores intermediate answers during computer run. Accumulator has two sets of outputs. The first set of output is two-state and is directly connected to Adder/Subtractor. The second set of output is a three-state and is directly connected to the W bus. Also called as the A Register.
B Register
B register is a part of ALU and another buffer register which contains the number to be added or subtracted to the contents of the accumulator.
Adder/Subtractor
The adder/subtractor is consists of two 4-bit full adder that can perform addition and subtraction(by using 2's complement).
Output Register Output register is the register that receives the processed data from the accumulator and drives the output display of SAP-1. Also called as output port because it processed data can leave the computer through this register. In microcomputers, the output ports are connected to interface circuits that drive peripheral devices.
Binary Display
The binary display is a row of 8 LEDs. Because the binary display is connected to the output port, it shows the contents of the processed data.
SAP-1 INSTRUCTION SET
SAP-1 Instruction Set A computer is a useless pile of hardware until someone programs it. Instruction set is the basic operation a computer can perform. SAP-1 Instruction set are LDA, ADD, SUB, OUT and HLT. These instructions are upward compatible with Intel 8080/8085(first widely used 8-bit microprocessor introduced in 1970). In other words, SAP-1 instructions are taken from Intel 8080/8085 instructions. Likewise, SAP-2 and SAP-3 instruction are also part of 8080/8085 instruction.
SAP-1 Instruction Set Abbreviated instructions(LDA, ADD, SUB, OUT, HLT) are called mnemonics. Mnemonic LDA ADD SUB OUT HLT
Operation Load RAM data into accumulator Add RAM data to accumulator Subtract RAM data from accumulator Load accumulator data into output register Stop processing
LDA LDA means ''LoaD the Accumulator''. A complete LDA instruction includes the address or memory location(written in hexadecimal to avoid confusion). Example:
LDA
8H
LDA 8H means ''Load the accumulator with the contents of memory location 8H''
ADD ADD is another SAP-1 instruction. A complete ADD instruction includes the address or memory location where given data is stored to be added. Example:
ADD
AH
ADD AH means ''ADD the contents of memory location AH to the contents of accumulator''.
SUB SUB is another SAP-1 instruction. A complete SUB instruction includes the address or memory location where given data is stored to be subtracted. Example:
SUB
CH
SUB CH means ''SUB the contents of memory location CH to the contents of accumulator''.
OUT The instruction OUT tells the SAP-1 computer to transfer the accumulator contents to the output port. OUT is complete by itself; that is you do not have to include an address or memory location when using OUT. Example:
OUT
HLT HLT means ''HaLT''. This instruction tells the computer to stop processing data. HLT marks the end of a program. It is necessary to use HLT instruction at the end of every SAP-1 program; otherwise, you will get a computer trash(meaningless answers caused by runaway processing). HLT is complete by itself; that is you do not have to include an address or memory location when using HLT. Example:
HLT
SAP-1 PROGRAMMING
SAP-1 Program
Example:
Create a SAP-1 program to solve this arithmetic problem: 10 + 5 +35 - 46
ADDRESS 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H
CONTENTS LDA 6H ADD 7H ADD 8H SUB 9H OUT HLT 0000 1010 0000 0101 0010 0011 0011 0010
SAP-1 Program To load the instruction and data word into SAP-1, we need to convert the source program(original program with mnemonics) into object program(program written in machine language). This means, instructions in mnemonic will be converted in operation code. Mnemonic LDA ADD SUB OUT HLT
Op code 0000 0001 0010 1110 1111
Example:
ADDRESS 0H 1H 2H 3H 4H
Translate the program into SAP-1 machine language. CONTENTS LDA 9H ADD AH SUB BH OUT HLT
LDA=0000 ADD=0001 SUB=0010 OUT=1110 HLT=1111
ADDRESS 0000 0001 0010 0011 0100
CONTENTS 0000 1001 0001 1010 0010 1011 1110 xxxx 1111 xxxx
SAP-1 MACHINE CYCLE
SAP-1 Machine Cycle The control unit is the key to a computer's automatic operation. The control unit generates the control words that fetch and execute each instructions. While each instructions is fetched and executed, the computer passes through different timing states(T states).
SAP-1 Timing States Timing states are binary words produced from a circuit counter called ring counter . Instead of counting binary numbers, a ring counter uses words that have only a single high bit. During a clock pulse, the output carries over the high bit into the next binary weight. For example, a ring counter has an initial output of 0001. Then during the next clock pulse, the next output would be 0010. After 0010 is 0100, 1000, 0001 0000 and so on.
SAP-1 Timing States The importance of ring counter is to control the sequence of operations by assigning it to different timing states. SAP-1 computer uses 6 different timing states. The first three states are called fetch cycle and the second three states are called execution states. T1 = T2 = T3 =
000001 000010 000100
T4 = T5 = T6 =
001000 010000 100000
SAP-1 Fetch cycle The T1 state is called the address state because the output of the program counter is transferred to the memory address register. During this state, the controller-sequencer sends out a CONTROL word: CON
= =
0101 1110 0011 5E3(simplified form)
SAP-1 Fetch cycle The T2 state is called increment state because the program counter is incremented. During this state, the controller-sequencer sends out a CONTROL word: CON
= =
1011 BE3
1110
0011
SAP-1 Fetch cycle The T3 state is called memory state because the addressed RAM instruction is transferred from the memory to the instruction register. During this state, the controller-sequencer sends out a CONTROL word: CON
= =
0010 263
0110
0011
SAP-1 Execution cycle
The T4, T5 and T6 are execution cycles. In these states, the instruction is carried out or performed. There are different execution cycles for each instructions. It is called microinstruction. For example, LDA has three microinstructions for each timing states. Microinstructions that were group together is called macroinstructions.
MACRO LDA
ADD
SUB
OUT
STATE T4 T5 T6 T4 T5 T6 T4 T5 T6 T4 T5 T6
CON 1A3 2C3 3E3 1A3 2E1 3C7 1A3 2E1 3CF 3F2 3E3 3E3
tate
T1 T2 T3 EXECUTION CYCLE T State T4 LDA T5 LDA T6 LDA T4 ADD T5 ADD T6 ADD T4 SUB T5 SUB T6 SUB T4 OUT
N 5E3 BE3 263
Act ve LM
EP CP CE LI
CON 1A3 2C3 3E3 1A3 2E1 3C7 1A3 2E1 3CF 3F2
Active LM EI CE L A none LM EI CE LB L A EU LM EI CE LB L A SU EU E A LO
