Preview only show first 10 pages with watermark. For full document please download

Silicon Photonics

silicon photonics

   EMBED


Share

Transcript

Silicon Photonics Opportunity, Applicatoins & Recent Results Mario Paniccia, Director Photonics Technology Lab Intel Corporation  Agenda  Opportunity for Silicon Photonics  Copper vs optical  Recent advances  Intels SP Research  Recent results  – Intel’s Silicon Laser   Summary ELECTRONICS: Moore’s Law Scaling MIPS Pentium ® 4 Processor  Pentium ® III Processor  Pentium ® II Processor  10000 1000 $/MIPS 100 10 Pentium ® Pro Processor  100 10 1 Pentium ®  Processor  Intel486TM DX CPU Intel386TM DX Microprocessor  Microprocessor  0.1 MIPS $/MIPS 1 0.01 1985 1987 1989 1991 1993 1995 1997 1999 2001 Integration & increased functionality Volume economics – faster, better, cheaper The Opportunity of Silicon Photonics  Take advantage of enormous ($ billions) CMOS infrastructure, process learning, and capacity  – Available tools: litho requirements typically >90nm  – Draft continued investment going forward  Potential to integrate multiple optical devices  Micromachini ng could provide smart packaging Micromachining  Potential to converge computing & communic communications ations Industry standard silicon manufacturing processes could enable optical. enableintegration, integration,bring bring“volume economics”totooptical. To benefit from existing infrastructure optical wafers must run alongside product.. i.e CMOS fabrication compatible.. Today's High Speed Interconnects Primarily Primarily Optical Copper  Chip to Chip 1 – 50 cm Metro & Long Haul Billions 0.1 – 80 km 0.1 – Board to Board 50 – 100 cm 50 – Rack to Rack V   o l     u m Millions  e  s 1 to 100 m Thousands Decreasing Distances Need to drive volume economics to drive optical closer to chip Copper Approaching Limits Simulation of 20” channel transmitter w/ equalization 0    ]    B    d    l    [   e   n   o   n   i   n   t   a   a    h   u    C  n   e    t    t    A 18G -10 Red Zone = Eye Closes -20 -30 12G -40 -50 Low Loss Ro4350 Standard FR4 0 10 20 30 40 Data Rate [Gb/s]  Copper scaling more challenging. Headroom getting squeezed. Howard Heck Electrical to Optical Enterprise Distance: 0.1-10km 10G Silicon Photonics? >= 40G OPTICAL Rack-Rack Distance: 1-100m 3.125G 10G 40G Optical Tech Board-Board Distance: 50-100cm 3.125G 5-6G Chip-Chip ELECTRICAL Distance: 1-50cm 3.125G 5-6G 2005 10G Copper Tech 20G T r a  an    s  i t  ti  i  o  on    Z o n  e  10G 15-20G 2010+ Transition driven by cost The Photonic Dilemma  Fiber has much more bandwidth than copper   However, it is much more expensive….. Photonics: The technology of emission, transmission, control and detection of light (photons) aka fiber -  optics & opto- electronics electronics Today: Most photonic devices made with exotic materials, expensive processing, complex packaging  Silicon Photonics Vision: Research effort to develop  photonic devices devices using using silicon as base material material and do this using standard, high volume silicon manufacturing techniques in existing fabs Benefit: Bring volume economics to optical communications communications  Agenda  Opportunity for Silicon Photonics  Copper vs optical  Recent advances  Intels SP Research  Recent results  – Intel’s Silicon Laser**  Summary Silicon Pro’s and Cons + Transparent in 1.3-1.6 µm region + CMOS fabrication compatibility + Low cost + High-index contrast – small footprint − − No electro-optic effect − − No detection in 1.3-1.6 µm region − − High index contrast – coupling − − Lacks efficient light emission Silicon will not win with passive devices.. Must produce active devices that add functionality Silicon Photonics Breakthroughs  Are Accelerating   Raman Net Pulsed Gain 9/6: Intel  9/20: Cornell  9/29: UCLA 9/29: CUHK  SRS UCLA Si LEDs STM, Trento Integrated   APD+TIA UT  Low Loss Strip Inverted Taper  NTT, Cornel  MIT  2001 2002  Raman Conversion UCLA 30GHz SiGe Photodetector  IBM  Modeled GHz PIN Modulator  GHz MOS Modulator  Intel  Surrey, Naples PBG WG  <25dB/cm PBG WG  <7dB/cm IBM  IBM, FESTA, NTT  2003 2004 Progress In Recent Years Is Accelerating still not there… CW Raman lasing Feb 05  Agenda  Opportunity for Silicon Photonics  Copper vs optical  Recent advances  Intel’s SP Research  Recent results  – Intel’s Silicon Laser**  Summary Intel’s Silicon Photonics Research 1. Develop photonic building blocks in silicon 1) Light Source 2) Guide Light 3) Modulation Waveguides devices First Continuous Silicon Laser  4) PhotoPhoto-detection 5) Low Cost Assembly Passive Align 6) Intelligence CMOS 1GHz (Nature ‘ 04) 04) 4 Gb/s ( ‘ ‘05)  05) (Nature 2/17/05) Mirror  SiGe Photodetectors First Prove that silicon is viable material for photonics Packaging Approximate Optical Product Cost Breakdown Packaging 1/3 Device 1/3 Testing 1/3 In addition to device costs, packaging and testing costs must drop with to enable high volume photonics Micromachining for Packaging Use standard pick and place technologies along with litho defined silicon micro -machining U-Grooves Tapers Mirror  V-Grooves Laser Attach 45° Mirrors Facet Preparation Intel’s Silicon Photonics Research 1. Develop photonic building blocks in silicon 2. Integrate increasing functionality directly onto silicon Integrated in Silicon Photodetectors DEMUX  Taper  Receiver  Chip Passive  Align Driver  Chip Lasers MUX  Intel’s Silicon Photonics Research 1. Develop photonic building blocks in silicon 2. Integrate increasing functionality directly onto silicon 3. Long term explore monolithic integration ECL Modulator  Filter  Multiple Channels   Drivers CMOS Circuitry TIA TIA Photodetector  Passive Alignment SILICON LASER What we announced on Feb 17th The First Laser Developed by Ted Maiman, published in Nature, August 6, 1960. this ruby laser used a flash lamp as an optical pump Fully Reflective Mirror  Flash Lamp Partially Reflective Mirror  LASER BEAM RUBY CRYSTAL ROD Raman: (Historical Note) Raman Effect or Raman Scattering: A phenomenon observed in the the scattering of light a it passes through a transparent medium; the light undergoes a change in frequency and random alteration alteration in phase due to a change in rotational or vibrational energy of the scattering molecules. • Disc Discover overed ed a mate material rial effe effect ct that that is name named d after after him him •Nature published his paper on the effect on March 31, 1928 •He received the Nobel prize in 1930 for his discovery • The first first lase laserr using using the the Raman Raman effect effect was built built in 1962 1962 • Today Raman based amplifiers are used throughout telecom • Most long distance phone calls will go through a Raman amplifier  Typical Raman Amplifier  The Raman Effect Materials Raman gain coefficient (10 -8 m/MW) Silicon Indium Antimonide (III-V) Quartz Lithium Niobate (used for modulators) Diamond Glass Fiber (Raman lasers/amps) 0 Kilometers of fiber  ... Centimeters of silicon 5000 10000 15000 20000 The Raman effect is 10,000 times stronger in silicon than in glass fiber  This allows for significant gain in centimeters instead of kilometers Fabrication of low-loss silicon waveguides is challenging Raman Gain in Silicon Silicon Waveguide Pump in Pump out Probe in Pump/probe experiment Probe out Raman Gain and WG loss vs. Input Pump Power  2.5 2.0    )    B    d    ( 1.5   n    i   a   g   n 1.0   a   m   a    R0.5 0.0 200 400 600 Input pump power(mW) 800 -0.2 3 -0.4   s   s   o    L 2.5    G    W    /    ) 2   n   B    i   a   d    (    G 1.5   n   a   m 1   a    R 0.5 (b) 0 3.5 1000 -0.6    )    B    d    ( -0.8   s   s   o    L -1     n    i   a -1.2    G Raman Gain WG Loss Loss w/o Pump Gain-Loss -1.4 0 -1.6 0 200 400 Pump Power (mW) 600 CW Gain Saturation due to TPA induced FCA Two Photon Absorption In silicon, one infrared photon doesn't have the energy to free an electron e e e e e Free e Electron e e e SILICON WAVEGUIDE But, occasionally, two photons can knock an electron out of orbit. Free electrons absorb individual photons and cancel Raman gain Overcoming TPA induced FCA  − V + laser beam p-type silicon   n    i   a    G   n   a   m   a    R electrons Gain needed to make a laser  oxide intrinsic silicon Gain limit due to Two Photon Absorption problem Pump power  n-type silicon SiO2 passivation  Al contact p-region  Lifetime=16 ns  Lifetime=6.8 ns  Lifetime=3.2 ns  Lifetime=1 ns 500 Si rib wav wavegu eguide ide H W Al contact h Buried oxide Si su subs bstr trat ate e n-region    ) 400    W   m    (   r 300   e   w   o   p    t 200   u   p    t   u    O100 25 V 5V short open 0 0 200 400 600 800 1000 1200 Input power (mW) PIN Cross-section TPA coeff ~ 0.5 cm/GW cm/GW,, 0.39 dB/cm dB/cm,, FCA cross sect 1.45e-17 1.45e-17 cm^2 cm^2 @ 1550 nm. nm. The lifetime is used as a fitting parameter CW gain vs. reverse bias voltage WG= ~1.5um by 1.5um NET GAIN NO NET GAIN Pump =1550 nm Signal =1686 nm With gain can build Laser: Silicon Waveguide Cavity 16 mm Rf  V bias n-region Rb   m   m    2 SOI rib waveguide Pump beam Laser output Dichroic coating 24%/71% p-region Broad-band reflective coating 90% Experimental setup Pump power monitor  Polarization controller  Pump at 1,550 nm Lensed fibre Silicon waveguide De-multiplexer  90/10 Tap coupler  LP filter  0 Optical spectrum analyzer  -10 -20 -30 -40 -50 -60 -70 -80 1684 1685 1686 1687 1688 1689 1690 1691 1692 90/10 Laser output power meter  Tap coupler  Laser  output at Dichroic 1,686 nm coating High reflection coating Experimental Set up Test chip with 8 laser WG’s Laser chip Typical Lasing Criteria •Threshold behavior:  rapid growth in output power when gain > loss •Spec •S pectr tral al lilinew newid idth th na narro rrowi wing ng::  Coherent light emission Threshold, Efficiency, and PIN effect 10.0 9.0 25V bia b ias s 8.0 5V bia b ias s    )    W 7.0   m    (    t 6.0   u   p 5.0    t   u   o   r 4.0   e   s 3.0   a    L 25V slope 5V slope 2.0 1.0 0.0 0 200 400 600 800 Coupled pump pu mp power (mW) (mW) Laser turns on at threshold, when gain per pass in cavity becomes greater than the loss. Spontaneous emission vs. laser spectrum 2.50 2.50    ) 2.00    )  . . 2.00   u   u  . .   a   a    (    (   r   r 1.50   e   e1.50   w   w   o   o   p   p    l    l 1.00   a   a   r   r 1.00    t    t   c   c   e   e   p   p    S    S0.50 0.50 0.00 0.00 11666688.5 .5 Lasing Lasingsignal signal Spontaneous Spontaneous emmission emmission Magnified 10^ 5x 11666699 11666699.5 .5 11667700 11667700.5 .5 Wavelength Wavelength (nm) (nm) When lasing, the spectrum becomes much more narrow and much higher in power. Wavelength tuning (comparison) 0 pump -10 0 -10 1548 nm -60    ) -20    B    d    (   r -30   e   w   o   p -40    l   a   r    t   c -50   a   p    S -70 -70 -80 -80    ) -20    B    d    (   r -30   e   w   o   p -40    l   a   r    t   c -50   a   p    S 1680 1550 nm 1552 nm 1554 nm 1556 nm 1558 nm 1548 nm 1550 nm 1552 nm 1554 nm 1556 nm 1558 nm -60 1685 1690 1695 Laser wavelength (nm) Silicon Raman laser 1700 1542 1547 1552 1557 Laser wavelength (nm) Commercial ECDL 1562 Potential Applications Communications Applications PUMP LASER Si Raman Amplifier  passively aligned waveguide coupler  weak data beam 101110 amplified data beam 101110 Si Multi-Channel Transmitter  silicon waveguide (cm’s) laser cavity P  modulators passively aligned MOD MUX PUMP LASER MOD MOD N  splitter  Si Raman Modulator  integrated mirrors MOD Optical Fiber  Covering the Gaps • Different wavelengths require different types of lasers • Mid-Infrared very difficult for compact semiconductors • Raman Lasers could enable lasers at these wavelengths • Applications in sensing, analysis, medicine, and others Compact  Semi. Lasers 2.1µm Ho:YAG laser  PUMP LASER >2   µ m 2.9µm Er:YAG laser  cascaded mirrors Could enable lasers for a variety of applications Summary Long term true convergence opportunities are with silicon B/W will continue drive conversion of optical into interconnects Tremendous progress from research community Need to continue pushing & improving performance Research breakthrough with CW silicon laser  Integration is next set of challenges In order to benefit Technologies must be CMOS fabrication compatible to benefit from HVM & infrastructure Silicon will not win with individual devices, but with integrate d modules that bring increased total functionality & intelligence at a lower cost BACKUP Benefits of Integration  Photonic Integration: Reduction in interfaces  – lower loss Reduction in size Simpler assembly, testing, packaging Cost Optoelectronic Integration: Reduce parasitics, improved high-freq performance Further size, testing, packaging reductions ? Cost Integration is only useful if integrated device has benefit (functionality,, cost, performance) over discrete devices (functionality CMOS Integration Challenges  – Film topology  – Coupling to fiber   – Contaminating the fab  – Yield metrology  – Thermal budgets  – Heat dissipation  – Complexity / yield Optoelectronic Integration To benefit from existing infrastructure optical wafers must run alongside product, introducing additional pragmatic challenges Surface Topology: Litho vs DOF • Depth of focus (DOF) shrinks as litho improves • Many optical devices are much taller than transistors For 0.18µm and better, topology exceeds DOF New planarization techniques required for advanced litho DOF vs. Litho Technology ( µm) 0.25 0.5 µm 0.18 0.35µm 0.09 Transistor  on 90nm 0.9µm Rib 0.2µm 0.2µ 0.3µm Strip 0.1µm gate 8µm Taper  Fiber Coupling Taper from (W x H): 10 x 8 µm to 2.5 x 2.3 µm  Assume zero roughness roughness  Tip=0.5  Tip=1.0  Tip=2.0 10    )    B    d    (   s   s   o    l   r 1   e   p   a    T • Coupling from standard fiber to Si waveguides requires special structures (tapers, gratings, etc). 2dB 1dB • For wedge tapers, etch angle as well as the tip lithography impact loss. 0.1 80 82 84 86 88 Sidewall angle (degrees) 90 • Sidewall roughness is also a factor Source: Intel Getting light from fibers into silicon waveguides will require couplers. For certain structures litho and etch parameters must be carefully controlled.  Yield Metrology • CMOS fabs monitor thousands of parameters across wafer in line • Tight control – e.g. CMOS gate width held to 10’s of angstroms • Significant per -  -wafer w   afer cost savings from screening out yield early • In-line wafer level optical probing is very immature • Most optical device testing is performed after wafer dicing To truly gain from HVM processing, automated & non-destructive techniques for probing optical devices at the wafer level must be developed Opto-Electronic Integration (cont) Thermal: Simulated multimulti-core thermal map For optoelectronic integration , optical devices must tolerate heat generated by CMOS circuits. IO Pads Core Core Other Logic Process compatibili compatibility: ty: @ 10Gb/s CMOS IC’s need 90nm technology Silicon Photonic devices may only need ~.25um Temp °C Cache Core Core IO Pads  Yield: Typical industry IC yields are high, but the process windows are extremely tight. Tweaks to enable opto-electronic opto-electronic integration may effect effect IC yield yield Trade off off of yield and and process compexi compexity ty will determi determine ne if opto-electrical integration valuable 80-85 75-80 70-75 65-70 60-65  Animation Click in box while in slide show mode to start Extending and Expanding Moore’s Law Sensors Mechanical Discrete SSI E X P Biological A EXTENDING D Fluidics I N G LSI   VLSI Wireless Optical Two Photon Absorption in Silicon Conduction band Silicon band gap 1.1 eV Pump λ=1.55µm Valence band Two photons can simultaneously hit an atom Combined energy enough to kick free an electron