Transcript
VHDL Reference Guide
Prepared by Digitronix Nepal
VHDL Reference Guide For Beginners Table of Contents: Design and Simulation of 1. Gate 2. MUX, Encoder 3. DeMUX, Decoder 4. Half Adder 5. Full Adder 6. ALU Design (2 –bit) 7. Latch , Flip-flops 8. Structural Design in VHDL: 8 bit ALU Design 9. Counter Design 10.Finite 10. Finite State Machine: Sequence Detector 11.File 11. File Handling in VHDL 12.Image 12. Image Processing in VHDL 13.Complete 13. Complete flow for Implementing design in Spartan 3e FPGA
1|Page For any Queries contact :
[email protected] or +977-9841078525
VHDL Reference Guide
Prepared by Digitronix Nepal
AND Gate
--VHDL Program of AND Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_gate_vhd is Port ( a : in STD_LOGIC; b : in STD_LOGIC; z : out STD_LOGIC); end and_gate_vhd; architecture Behavioral of and_gate_vhd is --signal declaration if have begin z<= a and b; end Behavioral;
RTL View of And Gate
Testbench of And Gate for Simulation
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY and_gate_tb IS 2|Page For any Queries contact :
[email protected] or +977-9841078525
VHDL Reference Guide END and_gate_tb;
Prepared by Digitronix Nepal
ARCHITECTURE behavior OF and_gate_tb IS COMPONENT and_gate_vhd PORT( a : IN std_logic; b : IN std_logic; z : OUT std_logic ); END COMPONENT;
--Inputs signal a : std_logic := '0'; signal b : std_logic := '0';
signal z : std_logic;
BEGIN -- Instantiate the Unit Under Test (UUT) uut: and_gate_vhd PORT MAP ( a => a, b => b, z => z ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; -- insert stimulus here a<='0'; b<='0'; wait for 100 ns; a<='0'; b<='1'; wait for 100 ns; a<='1'; b<='0'; wait for 100 ns; a<='1'; b<='1'; wait for 100 ns; wait; end process; END;
3|Page For any Queries contact :
[email protected] or +977-9841078525
VHDL Reference Guide
Prepared by Digitronix Nepal
Simulation Waveform of the AND Gate
For More Chapters Please Subscribe with Digitronix Nepal by
[email protected]
4|Page For any Queries contact :
[email protected] or +977-9841078525
